Receiver clock test circuitry and related methods and apparatuses

Patent metadata

Field	Value
Publication number	US-9294262-B2
Application number	US-201514722995-A
Country	US
Kind code	B2
Filing date	May 27, 2015
Priority date	May 2, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

First claim

We claim:

1. An integrated circuit, comprising:
a first receiver to receive a first signal from a first transmitter via a first transmission path and a first clock recovery circuit to generate a first recovered clock from the first signal for use in sampling the first signal during a normal mode of operation;
a second receiver to receive a second signal from a second transmitter via a second transmission path and a second clock recovery circuit to generate a second recovered clo…

Assignees

• Rambus Inc

Inventors

• Chandrasekaran Srinivasaraman
• Desai Kunal

Classifications

• H04L7/0083

  Electricity · mapped topic

• H04L1/242

  Electricity · mapped topic

• H04L7/0079 Primary

  Electricity · mapped topic

• H04L1/205 Primary

  Electricity · mapped topic

• G01R31/31709

  Physics · mapped topic