Crosstalk cancellation and/or reduction

Patent metadata

Field	Value
Publication number	US-9293798-B2
Application number	US-201113976780-A
Country	US
Kind code	B2
Filing date	Dec 19, 2011
Priority date	Dec 19, 2011
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

Some embodiments include a first differential signal pair and a second differential signal pair. The first and second differential signal pairs are arranged relative to each other in a manner to intentionally reduce or cancel crosstalk introduced by a pinout (for example, a section of a pinout, a socket, a connector, etc.) into at least one of the first differential signal pair and the second differential signal pair. Other embodiments are described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a pinout having pins;
a first microstrip differential signal pair; and
a second microstrip differential signal pair;
wherein the first microstrip differential signal pair and the second microstrip differential signal pair are connected to the pins and routed immediately after the pinout in a routing section,
and wherein the second microstrip differential signal pair is routed around the pinout to reverse polarities and brought closer to the first microstrip differential signal pair in the routing section to reduce crosstalk introduced to the second microstrip differential signal pair by the pinout,
and wherein signal lines of opposing polarity of the first microstrip differential signal pair and the second microstrip differential signal pair are arranged closest to each other in the pinout,
and wherein signal lines of a same polarity of the first microstrip differential signal pair and the second microstrip differential signal pair are arranged closest to each other in the routing section.

2. The apparatus of claim 1 , comprising microstrips of the first microstrip differential signal pair and the second microstrip differential signal pair that are routed near each other for specified portions of their lengths in an area near the pinout.

3. The apparatus of claim 2 , wherein the specified portions are just after the pinout.

4. The apparatus of claim 2 , wherein the specified portions are just before the pinout.

5. The apparatus of claim 1 , further comprising microstrip routing near each other for the first microstrip differential signal pair and the second microstrip differential signal pair in an area near the pinout.

6. The apparatus of claim 1 , further comprising routing in an area near the pinout a negative polarity signal of the first microstrip differential signal pair and a negative polarity signal of the second microstrip differential signal pair nearer to each other than any other signals of the first microstrip differential signal pair and the second microstrip differential signal pair.

7. The apparatus of claim 1 , further comprising routing in an area near the pinout a positive polarity signal of the first microstrip differential signal pair and a positive polarity signal of the second microstrip differential signal pair nearer to each other than any other signals of the first microstrip differential signal pair and the second microstrip differential signal pair.

8. The apparatus of claim 1 , wherein the first microstrip differential signal pair and the second microstrip differential signal pair comprise high-speed, serial links.

9. The apparatus of claim 1 , further comprising, in an area near the pinout, positions of negative and positive polarity signals of the first microstrip differential signal pair reversed.

10. The apparatus of claim 1 , wherein in an area near the pinout the negative polarity signal of the first microstrip differential signal pair is closer to the second microstrip differential signal pair than the positive polarity signal of the first microstrip differential signal pair, and wherein the negative polarity signal of the second microstrip differential signal pair is closer to the first microstrip differential signal pair than the positive polarity signal of the second microstrip differential signal pair.

11. The apparatus of claim 1 , wherein in an area near the pinout the positive polarity signal of the first microstrip differential signal pair is closer to the second microstrip differential signal pair than the negative polarity signal of the first microstrip differential signal pair, and wherein the positive polarity signal of the second microstrip differential signal pair is closer to the first microstrip differential signal pair than the negative polarity signal of the second microstrip differential signal pair.

12. The apparatus of claim 1 , further comprising a pin arrangement of a positive and a negative signal of a differential signal pair reversed on an additional pinout for one or more differential signal pairs on the additional pinout.

13. The apparatus of claim 1 , further comprising a pin arrangement of a positive and a negative signal of a differential signal pair reversed on a first pinout for one or more differential signal pairs on the connector relative to a corresponding near pin arrangement of a positive and a negative signal of a differential signal pair on a second pinout.

14. The apparatus of claim 1 , wherein the crosstalk is cancelled or reduced to an acceptable level.

15. The apparatus of claim 1 , wherein the pinout is a section of a pinout.

16. The apparatus of claim 1 , wherein the pinout is at least one of a connector, a socket, a section of a connector, a section of the socket, the connector and the socket, or a section of the connector and the socket.

17. An apparatus comprising:
a first pinout having a pin arrangement of a first plurality of microstrip differential signal pairs; and
a second pinout having a pin arrangement of a second plurality of microstrip differential signal pairs;
wherein the first pinout and the second pinout are routed immediately after a third pinout in a routing section,
and wherein the second pinout is routed around the third pinout to reverse polarities and brought closer to the first pinout in the routing section to reduce crosstalk introduced to the second pinout by the third pinout,
and wherein signal lines of opposing polarity of the first pinout and the second pinout are arranged closest to each other in the third pinout,
and wherein signal lines of a same polarity of the first pinout and the second pinout are arranged closest to each other in the routing section.

18. The apparatus of claim 17 , wherein a pin arrangement of a positive and a negative signal on one of the first plurality of microstrip differential signal pairs are reversed relative to a corresponding near pin arrangement of a positive and a negative signal of one of the second plurality of microstrip differential signal pairs.

19. The apparatus of claim 17 , wherein the first and second plurality of microstrip differential signal pairs comprise high-speed, serial links.

20. The apparatus of claim 17 , wherein the crosstalk is reduced to a predetermined threshold.

21. The apparatus of claim 17 , wherein the first pinout is a section of a fourth pinout.

22. The apparatus of claim 17 , wherein the first pinout is at least one of a connector, a socket, a section of the connector, a section of the socket, the connector and the socket, or a section of the connector and the socket.

Assignees

• Ye Xiaoning
• Intel Corp

Inventors

• Ye Xiaoning

Classifications

• H04L25/03878

  Line equalisers; line build-out devices · CPC title

• H05K1/0245

  Lay-out of balanced signal pairs, e.g. differential lines or twisted lines · CPC title

• H05K2201/10189

  Non-printed connector · CPC title

• H01P3/026

  Coplanar striplines [CPS] · CPC title

• H05K1/0228

  Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors (balanced signal pairs H05K1/0245) · CPC title