NAND EEPROM with perpendicular sets of air gaps and method for manufacturing NAND EEPROM with perpendicular sets of air gaps

Patent metadata

Field	Value
Publication number	US-9293547-B2
Application number	US-201113237425-A
Country	US
Kind code	B2
Filing date	Sep 20, 2011
Priority date	Nov 18, 2010
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device including memory cells comprising:
a semiconductor substrate;
a covered insulating film in a trench extending in a first direction, the trench dividing the semiconductor substrate into active regions adjacent to each other in a second direction crossing the first direction,
control gate electrodes extending in the second direction;
a select gate electrode extending in the second direction and adjacent to one of the control gate electrodes;
charge storage layers disposed between the control gate electrodes and the active regions, each one of the charge storage layers being provided for each one of the memory cells;
a select gate transistor disposed between one of the memory cells and a bit line, the select gate transistor having the select gate electrode; and
a gap provided between the adjacent charge storage layers in the second direction and extending continuously in the first direction, the gap being formed in the trench above the covered insulating film, extending beneath the select gate electrode, the gap terminating at a point directly beneath the select gate electrode;
wherein the covered insulating film exists in the trench below a part of the select gate electrode so as to line the portion of the gap extending beneath the select gate electrode.

2. The nonvolatile semiconductor memory device according to claim 1 , further comprising a space above the gap between word lines.

3. The nonvolatile semiconductor memory device according to claim 1 , further comprising a cover insulating film stretching over the control gate electrodes in a manner where the gap is preserved.

4. The nonvolatile semiconductor memory device according to claim 1 , wherein the gap is arranged in a manner where an interelectrode insulating film covers side walls of the charge storage layer.

5. The nonvolatile semiconductor memory device according to claim 1 , wherein assuming a gate length of the control gate electrode is L, and a height on the trench from an undersurface of an interelectrode insulating film to a top surface of the interelectrode insulating film on the charge storage layer is X, a depth D of the gap when viewed from the top surface of the interelectrode insulating film on the trench satisfies a condition of X+L/2≦D<2X+L.

6. The nonvolatile semiconductor memory device according to claim 1 , wherein the gap reaches to a position deeper than an undersurface of the charge storage layer.

7. The nonvolatile semiconductor memory device according to claim 1 , further comprising:
a bit contact part in which a bit contact is formed; and
a refilling insulating film filling a portion of the gap in a trench isolating an active area of the bit contact part.

8. The nonvolatile semiconductor memory device according to claim 1 , wherein an interelectrode insulating film is formed continuously over the adjacent memory cells in a word line direction in a manner of stretching over the gap.

9. The nonvolatile semiconductor memory device according to claim 8 , wherein the interelectrode insulating film is arranged in a position lower than a top of the charge storage layer on the gap.

10. A method for manufacturing a nonvolatile semiconductor memory device, comprising:
depositing a floating gate electrode material on a semiconductor substrate after interposing a tunnel insulating film;
forming a trench in the semiconductor substrate in a bit line direction through the floating gate electrode material and the tunnel insulating film;
forming a first insulating film in the trench;
forming an interelectrode insulating film on the first insulating film and the floating gate electrode material;
depositing a control gate electrode material on the interelectrode insulating film;
forming a floating gate electrode separated on a memory cell basis by patterning the control gate electrode material, the interelectrode insulating film, and the floating gate electrode material while forming both a control gate electrode arranged on the floating gate electrode in a word line direction and a select gate electrode; and
forming a gap arranged along the trench below bottoms of word lines between the adjacent floating gate electrode in the word line direction by removing at least a part of the first insulating film in the trench,
wherein
the gap is formed along the trench isolating an active area of both the memory cell and a select gate transistor and extending beneath the select gate electrode, and wherein
the gap terminates at a point directly below the select gate electrode, a portion of the first insulating film remaining in the trench below the select gate electrode so as to line the gap extending beneath the select gate electrode.

11. The method for manufacturing a nonvolatile semiconductor memory device according to claim 10 , further comprising forming a cover insulating film stretching over the control gate electrodes in a manner where the gap is preserved.

12. The method for manufacturing a nonvolatile semiconductor memory device according to claim 11 , further comprising a space above the gap between the word lines.

13. The method for manufacturing a nonvolatile semiconductor memory device according to claim 10 , wherein the interelectrode insulating film is formed continuously over the adjacent memory cells in the word line direction in a manner of stretching over the gap.

14. The method for manufacturing a nonvolatile semiconductor memory device according to claim 10 , further comprising refilling the gap formed in the trench isolating an active area of a bit contact part in which a bit contact is formed with a second insulating film after removing at least a part of the first insulating film in the trench.

15. A nonvolatile semiconductor memory device including memory cells comprising:
a semiconductor substrate;
a covered insulating film in a trench extending in a first direction, the trench dividing the semiconductor substrate into active regions adjacent to each other in a second direction crossing the first direction;
control gate electrodes extending in the second direction;
a select gate electrode extending in the second direction and adjacent to one of the control gate electrodes;
charge storage layers disposed between the control gate electrodes and the active regions, each of the charge storage layers being provided for each of the memory cells;
an interelectrode insulating film disposed between the control gate electrodes and the charge storage layers in the memory cells and disposed beneath the control gate electrodes and the select gate electrode above the trench;
a select gate transistor disposed between one of the memory cells and a bit line, the select gate transistor having the select gate electrode; and
a gap provided between the adjacent charge storage layers in the second direction and extending continuously in the first direction, the gap being formed in the trench above the covered insulating film and extending beneath the select gate electrode, the gap terminating at a point directly beneath the select gate electrode;
wherein the covered insulating film exists in the trench below a part of the select gate electrode so as to contact the interelectrode insulating film beneath the select gate electrode.

Assignees

• Arai Fumitaka
• Sakamoto Wataru
• Kikushima Fumie
• Nitta Hiroyuki
• Toshiba Kk

Inventors

• Arai Fumitaka
• Sakamoto Wataru
• Kikushima Fumie
• Nitta Hiroyuki

Classifications

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/021

  of air gaps · CPC title