Non-data inclusive coherent (NIC) directory for cache

Patent metadata

Field	Value
Publication number	US-9292445-B2
Application number	US-201414501437-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Mar 5, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.

First claim

What is claimed is:

1. A computer implemented method for operation of a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer, the method comprising:
determining a first eviction entry of a highest-level cache in a multilevel caching structure of a first processor node of the SMP;
determining that the NIC directory is not full;
determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure;
based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory; and
invalidating the first eviction entry in the highest-level cache;
determining a second eviction entry in the lower-level cache in the multilevel caching structure;
determining that an entry corresponding to the second eviction entry is located in the NIC directory;
determining that an entry corresponding to the second eviction entry is not located in another lower-level cache in the multilevel caching structure;
based on the entry corresponding to the second eviction entry being located in the NIC directory and based on no entry corresponding to the second eviction entry being located in another lower-level cache of the multilevel caching structure, creating a second new entry corresponding to the second eviction entry in the highest-level cache; and
invalidating the entry corresponding to the second eviction entry in the NIC directory.

2. The method of claim 1 , further comprising:
setting the second new entry in the highest-level cache to a most recently used (MRU) position; and
setting an ownership of the second new entry in the highest-level cache to unowned.

3. The method of claim 1 , further comprising:
based on the NIC directory being full and based on a least recently used (LRU) unowned entry existing in the highest-level cache, evicting to a main memory of the computer system the LRU unowned entry; and
based on the NIC directory being full and based on a least recently used (LRU) unowned entry not existing in the highest-level cache, evicting an LRU owned entry of the highest-level cache to the main memory of the computer system.

4. The method of claim 1 , further comprising:
receiving a snoop by the first processor node from a second processor node of the SMP via a SMP bus;
determining that an entry corresponding to the snoop is located in the NIC directory;
retrieving data corresponding to the snoop from the lower-level cache; and
forwarding the retrieved data to the second processor node via the SMP bus.

5. The method of claim 4 , wherein the snoop comprises an exclusive snoop, and further comprising:
invalidating the entry corresponding to the exclusive snoop in the NIC directory.

6. The method of claim 4 , wherein the snoop comprises a shared snoop, and further comprising:
updating to shared ownership of the entry corresponding to the shared snoop in the NIC directory.

7. The method of claim 1 , wherein the highest-level cache and the NIC directory are in communication with a plurality of lower-level caches in the multilevel caching structure;
wherein the highest-level cache comprises a directory comprising entries corresponding to a first plurality of addresses, and data associated with the first plurality of addresses in the directory; and
wherein the NIC directory comprises entries corresponding to a second plurality of addresses, and wherein the NIC directory does not comprise data associated the second plurality of addresses.

8. The method of claim 1 , wherein determining the first eviction entry of the highest-level cache of the first processor node of the SMP comprises:
based on an entry that is exclusively owned by the lower-level cache existing in the highest-level cache, selecting the entry that is exclusively owned by the lower-level cache as the first eviction entry;
based on an entry that is exclusively owned by the lower-level cache not existing in the highest-level cache, and based on a shared entry having an unset intervention master (IM) tag existing in the highest-level cache, selecting the shared entry having the unset IM tag as the first eviction entry; and
based on a shared entry having an unset IM tag not existing in the highest-level cache, selecting a shared entry having a set IM tag as the first eviction entry.

9. A computer program product for implementing a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer, the computer program product comprising:
a tangible non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
determining a first eviction entry of a highest-level cache in a multilevel caching structure of a first processor node of the SMP;
determining that the NIC directory is not full;
determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure;
based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory; and
invalidating the first eviction entry in the highest-level cache;
determining a second eviction entry in the lower-level cache in the multilevel caching structure;
determining that an entry corresponding to the second eviction entry is located in the NIC directory;
determining that an entry corresponding to the second eviction entry is not located in another lower-level cache in the multilevel caching structure;
based on the entry corresponding to the second eviction entry being located in the NIC directory and based on no entry corresponding to the second eviction entry being located in another lower-level cache of the multilevel caching structure, creating a second new entry corresponding to the second eviction entry in the highest-level cache; and
invalidating the entry corresponding to the second eviction entry in the NIC directory.

10. The computer program product of claim 9 , further comprising:
setting the second new entry in the highest-level cache to a most recently used (MRU) position; and
setting an ownership of the second new entry in the highest-level cache to unowned.

11. The computer program product of claim 9 , further comprising:
based on the NIC directory being full and based on a least recently used (LRU) unowned entry existing in the highest-level cache, evicting to a main memory of the computer system the LRU unowned entry; and
based on the NIC directory being full and based on a least recently used (LRU) unowned entry not existing in the highest-level cache, evicting an LRU owned entry of the highest-level cache to the main memory of the computer system.

Assignees

• IBM

Inventors

• Bronson Timothy C
• Drapala Garrett M
• Gott Rebecca M
• Mak Pak-Kin
• Srinivasan Vijayalakshmi
• Walters Craig R

Classifications

• G06F12/0833 Primary

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F2212/283

  Plural cache memories · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title