Mems apparatus with anti-stiction layer
US-2020346919-A1 · Nov 5, 2020 · US
US9290380B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9290380-B2 |
| Application number | US-201213718614-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 18, 2012 |
| Priority date | Dec 18, 2012 |
| Publication date | Mar 22, 2016 |
| Grant date | Mar 22, 2016 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A mechanism for reducing stiction in a MEMS device by decreasing surface area between two surfaces that can come into close contact is provided. Reduction in contact surface area is achieved by increasing surface roughness of one or both of the surfaces. The increased roughness is provided by forming a micro-masking layer on a sacrificial layer used in formation of the MEMS device, and then etching the surface of the sacrificial layer. The micro-masking layer can be formed using nanoclusters. When a next portion of the MEMS device is formed on the sacrificial layer, this portion will take on the roughness characteristics imparted on the sacrificial layer by the etch process. The rougher surface decreases the surface area available for contact in the MEMS device and, in turn, decreases the area through which stiction can be imparted.
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a microelectromechanical systems (MEMS) device, the method comprising: forming a first polysilicon layer over a substrate; forming a sacrificial layer over the first polysilicon layer; forming a plurality of nanoclusters on the sacrificial layer; etching the sacrificial layer using a wet etch process subsequent to said forming the plurality of nanoclusters, wherein the wet etch is selective to the sacrificial layer, the nanoclusters provide a micro-masking layer for said etching, and said etching increases roughness of the surface of the sacrificial layer as compared to the roughness of the surface upon said forming the sacrificial layer; removing the nanoclusters from the surface of the sacrificial layer; and forming a second polysilicon layer on the sacrificial layer subsequent to said etching the sacrificial layer, wherein said removing is performed subsequent to said etching and prior to said forming the second polysilicon layer. 2. The method of claim 1 , wherein the nanoclusters comprise germanium, and said removing is performed using a peroxide etch. 3. The method of claim 1 wherein said nanoclusters comprise one of silicon or germanium. 4. The method of claim 1 wherein said forming the plurality of nanoclusters comprises: performing a low temperature deposition of nanocluster material; and performing an anneal to form the nanoclusters. 5. The method of claim 4 wherein said performing the low temperature deposition of nanocluster material further comprises: depositing sufficient material to form nanoclusters having a diameter of approximately 20 nm or greater upon performing said annealing. 6. The method of claim 1 further comprising: forming a first insulating layer over the substrate, wherein the first polysilicon layer is formed over the first insulating layer; forming a second insulating layer over at least a portion of the first polysilicon layer, wherein the sacrificial layer is further formed over the second insulating layer. 7. The method of claim 1 further comprising: removing the sacrificial layer using a wet etch process subsequent to said forming the second polysilicon layer. 8. The method of claim 7 , wherein the second polysilicon layer comprises a plurality of surface roughness features having a height of between about 25 nm to about 50 nm.
For avoiding stiction when the device is in use, i.e. after manufacture has been completed · CPC title
Structures having a reduced contact area, e.g. with bumps or with a textured surface · CPC title
See-saws · CPC title
using stopper structures for limiting the travel of the seismic mass · CPC title
Anti-stiction coatings · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.