Anti-stiction process for MEMS device

US10513432B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10513432-B2
Application numberUS-201815904085-A
CountryUS
Kind codeB2
Filing dateFeb 23, 2018
Priority dateJul 31, 2017
Publication dateDec 24, 2019
Grant dateDec 24, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, the method comprising the steps of: providing a first wafer; treating the first wafer to form cavities and at least one oxide layer on a top surface of the first wafer using a first chemical vapor deposition process; providing a second wafer; bonding the second wafer on a top surface of the at least one oxide layer; treating the second wafer to form a first plurality of structures, wherein treating the second wafer further comprises etching a layer of germanium over the second wafer to form a second plurality of structures; and depositing a layer of Self-Assembling Monolayer (SAM) to a surface of a micro electro-mechanical system (MEMS) component using a second chemical vapor deposition process. 2. The method of claim 1 , wherein the step of treating the first wafer further comprises the step of: etching the first wafer to create a first plurality of upward facing cavities. 3. The method of claim 2 , wherein the step of treating the first wafer further comprises the step of: depositing an oxide layer on the top of the first wafer with the first plurality of the upward facing cavities using the first chemical vapor deposition process, wherein the first chemical vapor contains at least the oxide. 4. The method of claim 1 , wherein the step of treating the second wafer further comprises the step of: fusing the second wafer on a top of the at least one oxide layer; and etching the second wafer to form the second plurality of structures. 5. The method of claim 1 , wherein the step of treating the second wafer further comprises the step of: depositing the layer of germanium over the second wafer using a physical vapor deposition process. 6. The method of claim 1 , wherein the step of treating the second wafer further comprises the step of: etching the second wafer to form a plurality of MEMS actuators. 7. The method of claim 6 , further comprises the step of: treating the MEMS component by maintaining a temperature at a constant value for a period of time to partially remove the layer of SAM on the layer of germanium. 8. The method of claim 7 , wherein the temperature is in a range of 430 to 490 degrees Celsius. 9. The method of claim 7 , wherein the period of time is in a range of 30 to 240 minutes. 10. The method of claim 7 , further comprises the step of: wet etching the MEMS component to completely remove the layer of SAM on the layer of germanium. 11. The method of claim 10 , further comprises the step of: bonding the MEMS component to a complementary metal-oxide-semiconductor (CMOS) wafer using eutectic bonding. 12. A process, the process comprising the steps of: providing a micro electro-mechanical system (MEMS) component that comprises a layer of germanium; depositing a layer of Self-Assembling Monolayer (SAM) to the MEMS component using a chemical vapor deposition process; and maintaining a temperature of the MEMS component at a value for a period of time to partially remove the layer of SAM on the layer of germanium. 13. The process of claim 12 , further comprises the step of: wet etching the MEMS component to completely remove the layer of SAM on the layer of germanium. 14. The process of claim 13 , further comprises the step of: bonding the MEMS component to a CMOS wafer using eutectic bonding. 15. The process of claim 12 , wherein the temperature is in a range of 430 to 490 degrees Celsius. 16. The process of claim 12 , wherein the period of time is in a range of 30 to 240 minutes. 17. A method, comprising: providing a micro electro-mechanical system (MEMS) component that comprises a layer of germanium; depositing a layer of Self-Assembling Monolayer (SAM) to the MEMS component; and wet etching the MEMS component to completely remove the layer of SAM on the layer of germanium. 18. The method of claim 17 , further comprising: bonding the MEMS component to a CMOS wafer. 19. The method of claim 18 , wherein the MEMS component is bonded to the CMOS wafer based on a eutectic bonding. 20. The method of claim 17 , wherein the layer of SAM is deposited based on a chemical vapor deposition process.

Assignees

Inventors

Classifications

  • Monolayers · CPC title

  • Deposited materials, e.g. layers · CPC title

  • Bonding a wafer on the substrate, i.e. where the cap consists of another wafer · CPC title

  • Depositing an anti-stiction or passivation coating, e.g. on the elastic or moving parts · CPC title

  • involving bonding one or several substrates on a non-temporary support, e.g. another substrate · CPC title

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What does patent US10513432B2 cover?
A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the …
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification B81C1/00015. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Dec 24 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).