Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9287400-B2
Application number	US-201213587361-A
Country	US
Kind code	B2
Filing date	Aug 16, 2012
Priority date	Oct 22, 2007
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on other side thereof, and a gate electrode formed between said source region and said drain region to surround said fin-shaped semiconductor portion with a gate insulating film interposed therebetween, the method for manufacturing a semiconductor device comprising the steps of:
forming an insulating film on a semiconductor layer and further forming a film of amorphous silicon;
patterning said amorphous silicon in a predetermined shape and performing a short-time thermal treatment on said amorphous silicon to crystallize said amorphous silicon;
forming a sidewall on a side face of said amorphous silicon crystallized;
sequentially etching said insulating film and said semiconductor layer, using as a mask said sidewall from which said amorphous silicon is removed, to form said fin-shaped semiconductor portion;
forming a first dummy pattern upon forming said fin-shaped semiconductor portion; and
forming a second dummy pattern upon forming said gate electrode,
wherein said first dummy pattern is positioned under said second dummy pattern,
said first dummy pattern is separated from said fin-shaped semiconductor portion,
said second dummy pattern is separated from said gate electrode, and
said second dummy pattern does not overlap said first dummy pattern.

2. A method for manufacturing a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on other side thereof, and a gate electrode formed between said source region and said drain region to surround said fin-shaped semiconductor portion with a gate insulating film interposed therebetween, the method for manufacturing a semiconductor device comprising the steps of:
forming an insulating film on a semiconductor layer and further forming a film of amorphous silicon;
reducing unevenness of a surface of said amorphous silicon;
patterning said amorphous silicon having the surface with reduced unevenness in a predetermined shape;
forming a sidewall on a side face of said amorphous silicon patterned;
sequentially etching said insulating film and said semiconductor layer, using as a mask said sidewall from which said amorphous silicon is removed, to form said fin-shaped semiconductor portion;
forming a first dummy pattern upon forming said fin-shaped semiconductor portion; and
forming a second dummy pattern upon forming said gate electrode,
wherein said first dummy pattern is positioned under said second dummy pattern,
said first dummy pattern is separated from said fin-shaped semiconductor portion,
said second dummy pattern is separated from said gate electrode, and
said second dummy pattern does not overlap said first dummy pattern.

3. The method for manufacturing a semiconductor device according to claim 2 , wherein said step of reducing unevenness of the surface of said amorphous silicon sacrificially oxidizes the surface of said amorphous silicon and thereafter removes an oxidized film in question to reduce the unevenness.

Assignees

• Iwamatsu Toshiaki
• Terada Takashi
• Shinohara Hirofumi
• Ishikawa Kozo
• Tsuchiya Ryuta
• Hayashi Kiyoshi
• Renesas Electronics Corp

Inventors

• Iwamatsu Toshiaki
• Terada Takashi
• Shinohara Hirofumi
• Ishikawa Kozo
• Tsuchiya Ryuta
• Hayashi Kiyoshi

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P30/208

  of electrically inactive species · CPC title