Global shutter bulk charge modulated device

Patent metadata

Field	Value
Publication number	US-9287305-B2
Application number	US-201514589520-A
Country	US
Kind code	B2
Filing date	Jan 5, 2015
Priority date	Jan 31, 2011
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

The invention describes image sensor array pixels with global and rolling shutter capabilities that utilize multiple BCMD transistors for storing and sensing charge for a single photodiode. This configuration improves the Dynamic Range (DR) of the sensor, by allowing sensing different image signals from a single pixel without saturation, a low level signal with long integration time followed by a high level signal with short integration time. Signal processing circuits can process these signals into a single Wide Dynamic Range (WDR) output. Further disclosed are pixels that use multiple-gate BCMD transistors for charge storage and sensing having multiple concentric gates, which allows changing the conversion gain of the BCMD transistors. Variable conversion gain is a useful feature when building WDR sensors since low conversion gain and high well capacity allows detection of high level signals and, at the same time, low level signals with high conversion gain and low noise.

First claim

What is claimed is:

1. A CMOS image sensor pixel array that includes at least one pixel circuit, comprising:
at least one concentric dual gate Bulk Charge Modulated Device (BCMD) transistor coupled to a single photodiode, wherein the at least one concentric dual gate BCMD transistor is operable to store charge transferred from the photodiode for all the pixels of the array simultaneously, wherein the stored charge is accumulated in at least one integration time, wherein the at least one concentric dual gate BCMD comprises an inner ring gate and an outer ring gate, and wherein the outer ring gate completely surrounds the inner ring gate; and
peripheral circuitry, wherein the at least one concentric dual gate BCMD transistors are additionally operable to be subsequently addressed and scanned in a row by row manner.

2. The CMOS image sensor array of claim 1 , wherein the at least one concentric dual gate BCMD transistors are operable to store charge transferred from the photodiode for all the pixels of the array in a row by row manner.

3. The CMOS image sensor of claim 2 , wherein the least one concentric dual gate BCMD transistors include independently addressed input and reset gates.

4. The CMOS image sensor array of claim 2 , wherein the photodiode is coupled to a JFET anti-blooming structure to drain away any overflow charge.

5. The CMOS image sensor array of claim 2 , wherein the photodiode is coupled to a MOSFET anti-blooming structure to drain away any overflow charge.

6. The CMOS image sensor array of claim 2 , wherein the peripheral circuitry performs a signal differencing function on the charge accumulated in the photodiode during at least two different integration times, thus providing for detection of intra-scene motion.

7. The CMOS image sensor of claim 1 , wherein the at least one concentric dual gate BCMD transistors include independently addressed input and reset gates.

8. The CMOS image sensor pixel array of claim 1 , wherein the photodiode is coupled to a JFET anti-blooming structure to drain away any overflow charge.

9. The CMOS image sensor array of claim 1 , wherein said photodiode is coupled to a MOSFET anti-blooming structure to drain away any overflow charge.

10. The CMOS image sensor array of claim 1 , wherein the peripheral circuitry performs a signal differencing function on said charge accumulated in said photodiode during at least two different integration times, thus providing for detection of intra-scene motion.

11. An array of image pixels each of which comprises:
a multiple gate Bulk Charge Modulated Device (BCMD) device that comprises:
a p+ type substrate layer;
a p type epi-layer formed on the p+ type substrate layer;
an n type well formed in the p type epi-layer;
an oxide layer that partially covers the n type well and the p type epi-layer;
a p+ type doped region in the n type well, wherein the p+ type doped region comprises a source region;
a plurality of gate contacts that are formed on the oxide layer, wherein the oxide layer is formed between the gate contacts and the p+ type substrate layer, wherein at least two of the gate contacts are concentric circular gates, and wherein the source region is positioned in the center of the concentric circular gates; and
a drain region in the n type well that changes in size based on the bias voltages applied to the plurality of gate contacts.

12. The image pixel defined in claim 11 , wherein the at least two concentric circular gates comprise first and second circular gates with respective first and second diameters, wherein the first diameter is less than the second diameter, and wherein the effective gate area of the BCMD transistor changes based on respective first and second bias voltages applied to the first and second circular gates.

13. The image pixel defined in claim 11 , wherein the BCMD device is coupled to only one photodiode.

14. The image pixel defined in claim 13 , wherein the photodiode is coupled to a JFET anti-blooming structure to drain away any overflow charge.

15. The CMOS image pixel defined in claim 13 , wherein the photodiode is coupled to a MOSFET anti-blooming structure to drain away any overflow charge.

16. An image pixel, comprising:
a multi-gate Bulk Charge Modulated Device (BCMD) that comprises:
first and second circular gate contacts that are formed on an oxide layer, wherein the first and second gate contacts are concentric, wherein the oxide layer is formed between the gate contacts and a semiconductor substrate, wherein the first and second circular gate contacts have respective first and second diameters, wherein the first diameter is less than the second diameter, and wherein the BCMD is operable in a high conversion gain mode when the second circular gate contact is biased at a low voltage level.

17. The image pixel defined in claim 16 , wherein the BCMD device is operable in a low conversion gain mode when the first and second circular gate contacts are biased at a common voltage.

Assignees

• Semiconductor Components Ind

Inventors

• Hynecek Jaroslav
• Agranov Gennadiy
• Li Xiangli
• Komori Hirofumi
• Zhao Xia
• Wan Chung Chun

Classifications

• H04N25/621

  for the control of blooming · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/771

  comprising storage means other than floating diffusion · CPC title

• H10F39/1865

  Overflow drain structures · CPC title

• H10F39/196

  Junction field effect transistor [JFET] image sensors; Static induction transistor [SIT] image sensors · CPC title