Method for manufacturing a semiconductor device comprising transistors each having a different effective work function

Patent metadata

Field	Value
Publication number	US-9287273-B2
Application number	US-201514733880-A
Country	US
Kind code	B2
Filing date	Jun 8, 2015
Priority date	Jun 6, 2014
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

The disclosed technology generally relates a semiconductor device comprising transistors, and more particularly to a semiconductor device comprising transistors each having a gate stack with a different effective work function, and methods of fabricating such a device. In one aspect, the method of fabricating the semiconductor comprises providing at least two channel regions in the substrate and providing a dielectric layer on the substrate. The method additionally includes forming a plurality of gate regions by providing openings in the dielectric layer. The method further includes providing a gate dielectric layer in the openings and providing on the gate dielectric layer of each of the gate regions a barrier layer stack having different thickness along the different gate regions.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device comprising transistors each having a different work function arranged along a main surface of a substrate, the method comprising:
providing at least two channel regions in the substrate;
providing a dielectric layer on the substrate over the at least two channel regions;
providing openings through the dielectric layer to expose portions of each of the at least two channel regions, thereby defining corresponding gate regions inside the openings and over the at least two channel regions;
providing a gate dielectric layer on the exposed channel regions of each of the gate regions;
providing on the gate dielectric layer of each of the gate regions a barrier layer stack each having a different thickness,
wherein providing the barrier layer stack comprises:
providing a first barrier layer on the gate dielectric layer of each of the gate regions;
selectively removing the first barrier layer from a subset of the gate regions while leaving the first barrier layer in at least a complementary subset of the gate regions;
repeating at least once the processes of:
providing a subsequent barrier layer in each of the gate regions;
selectively removing the subsequent barrier layer from a respective subset of the channel regions, while leaving the respective subsequent barrier layer in a respective complementary subset of the channel regions, such that barrier layer stacks having different thickness along different gate regions are provided; and

providing a gate-filling stack of metal layers on the barrier layer stack in each of the gate regions.

2. The method according to claim 1 , wherein providing the barrier layer comprises repeating only once the processes of:
providing a subsequent barrier layer in each of the gate regions;
selectively removing the subsequent barrier layer from a respective subset of the channel regions, while leaving the respective subsequent barrier layer in a respective complementary subset of the channel regions.

3. The method according to claim 1 , wherein providing the barrier layer comprises repeating only twice the processes of:
providing a subsequent barrier layer in each of the gate regions;
selectively removing the subsequent barrier layer from a respective subset of the channel regions, while leaving the respective subsequent barrier layer in a respective complementary subset of the channel regions.

4. The method according to claim 1 , wherein the first barrier layer and the subsequent barrier layer comprise one or both of TiN and TaN.

5. The method according to claim 1 , wherein the first barrier layer and the subsequent barrier layer are formed of the same material.

6. The method according to claims 1 , wherein the first barrier layer and the subsequent barrier layer are formed of a different material.

7. The method according to claim 1 , wherein providing the gate-filling stack of metal layers comprises providing a metal selected from the group consisting of TiN, TiAl, Al, TiC, Co, W and combinations thereof.

8. The method according to claim 7 , wherein providing the gate-filling stack of metal layers comprises providing a metal layer formed of TiAl or Al and further comprises:
providing a TiN layer on the metal layer;
patterning the TiN layer above at least one gate region;
selectively removing the metal layer from at least one gate region by using the patterned TiN layer as a mask; and
providing a further metal layer of the gate filling stack of metal layers in the at least one gate region.

9. The method according to claim 8 , wherein patterning the TiN layer comprises resist patterning.

10. The method according to claim 1 , further comprising performing a flattening step on the substrate, up until a level defined by the dielectric layer.

11. The method according to claim 1 , wherein the exposed portions of the at least two channel regions define channel lengths smaller than 20 nm of the transistors.

12. The method according to claim 1 , wherein providing the first barrier layer or the subsequent barrier layer comprises depositing using atomic layer deposition (ALD).

Assignees

• Imec Vzw

Inventors

• Ragnarsson Lars-Ake
• Schram Tom
• Dekkers Hendrik F W
• Chew Soon Aik

Classifications

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/014 Primary

  the gate conductors having different materials or different implants · CPC title