Semiconductor package

Patent metadata

Field	Value
Publication number	US-9287220-B2
Application number	US-201414249080-A
Country	US
Kind code	B2
Filing date	Apr 9, 2014
Priority date	Jun 28, 2013
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

Disclosed herein is a semiconductor package. The semiconductor package according to a preferred embodiment of the present invention includes: a first substrate having an electronic device mounted on both surfaces thereof; and a second substrate bonded to one surface of the first substrate and including an insertion part in which the electronic device mounted on one surface of the first substrate is inserted, wherein the second substrate includes a ground and a shielding wall which is formed along an inner wall or an outer wall of the second substrate.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first substrate having an first electronic device mounted on one surface of the first substrate and a second electronic device mounted on another surface of the first substrate facing the one surface;
a first molding part sealing the second electronic device;
a first shielding film formed on an external surface of the first molding part; and
a second substrate bonded to the one surface of the first substrate and including an insertion part in which the first electronic device mounted on the one surface of the first substrate is inserted,
wherein the second substrate includes a ground via, a first shielding wall which is formed along an inner wall of the second substrate, and
a ground pattern connecting the ground via with the first shielding wall,
wherein the first substrate includes a ground layer formed therein and connected to the first shielding film and the ground via,
wherein the first electronic device includes at least one of a passive device and an active device, and
wherein the second electronic device includes at least one of a passive device and an active device.

2. The semiconductor package as set forth in claim 1 ,
wherein the ground layer is formed to have both ends exposed to an outside of the first substrate.

3. The semiconductor package as set forth in claim 1 , wherein the second substrate further includes a signal via.

4. The semiconductor package as set forth in claim 1 , wherein in the shielding wall, a region corresponding to a position at which the signal via is formed is opened.

5. The semiconductor package as set forth in claim 4 , further comprising:
a shielding via formed at the position corresponding to the opened region of the first shielding wall and formed on a straight line, along with the signal via.

6. The semiconductor package as set forth in claim 1 , wherein the insertion part has a through hole form.

7. The semiconductor package as set forth in claim 1 , wherein the insertion part has a groove form.

8. The semiconductor package as set forth in claim 7 , wherein a bottom surface in the insertion part is further provided with the first shielding wall.

9. The semiconductor package as set forth in claim 1 , wherein the first substrate is further provided with a circuit layer.

10. The semiconductor package as set forth in claim 1 , wherein the second substrate further includes a conductive via which is electrically connected to the first substrate.

11. The semiconductor package as set forth in claim 10 , further comprising:
an external connection terminal formed on one surface of the second substrate and connected to the conductive via.

12. The semiconductor package as set forth in claim 6 , further comprising:
a second molding part formed in the insertion part to seal the first electronic device.

13. The semiconductor package as set forth in claim 12 , further comprising:
a second shielding film formed on one surface of the second molding part and electrically connected to the shielding wall.

14. The semiconductor package as set forth in claim 7 , further comprising:
a second molding part formed in the insertion part to seal the first electronic device.

15. The semiconductor package as set forth in claim 1 , further comprising:
a second shielding wall formed on an outer wall of the second substrate.

16. The semiconductor package as set forth in claim 13 , wherein the first shielding film has a lattice form.

Assignees

• Samsung Electro Mech

Inventors

• Nam Yun Tae

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/657

  on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title