Semiconductor memory

Patent metadata

Field	Value
Publication number	US-9286949-B2
Application number	US-201414303462-A
Country	US
Kind code	B2
Filing date	Jun 12, 2014
Priority date	Jul 18, 2013
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A semiconductor memory includes a memory cell array having a plurality of memory cells, a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array, and a sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for amplifying a potential difference between the bit line pair, in which the sense amplifier has precharging transistors each having a diffusion layer and precharging the bit line pair, and switching transistors having a diffusion layer formed integrally with the diffusion layer of the precharging transistors for selectively connecting the plurality of bit line pairs to a common bus line.

First claim

What is claimed is:

1. A semiconductor memory comprising:
a memory cell array having a plurality of memory cells;
a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array; and
sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for amplifying a potential difference between the bit line pair,
wherein the sense amplifier includes:
precharging transistors each having a diffusion layer and precharging the bit line pair; and
switching transistors each having a diffusion layer formed integrally with the diffusion layer of the precharging transistor for selectively connecting the plurality of the bit line pairs to a common bus line.

2. A semiconductor memory according to claim 1 , wherein
the gate of the switching transistor has a longitudinal direction along a vertical direction perpendicular to the bit line direction.

3. The semiconductor memory according to the claim 2 , further comprising:
an amplifier portion including at least two transistors connected to the bit line pair for amplifying the potential difference between the bit line pair,
wherein the sense amplifier pitch of the sense amplifier is defined by the width of the amplifier portion in the vertical direction,
wherein the sense amplifier is disposed repeatedly at the sense amplifier pitch in the vertical direction, and
wherein the gate of the switching transistor extends to an adjacent sense amplifier pitch.

4. The semiconductor memory according to claim 3 ,
wherein the longitudinal direction of the gate of the precharging transistor is along a vertical direction, and
wherein the gate of the precharging transistor extends to the adjacent sense amplifier pitch.

5. The semiconductor memory according to claim 3 , wherein
the diffusion layer extends to the adjacent sense amplifier pitch.

6. The semiconductor memory according to claim 5 , wherein
the diffusion layers are formed integrally in the two sense amplifiers adjacent in the vertical direction.

7. The semiconductor memory according to claim 6 , wherein
the common bus line is connected to the diffusion layer being shared by the two sense amplifiers adjacent in the vertical direction.

8. The semiconductor memory according to claim 2 ,
wherein the precharging transistor includes an equalizing transistor for equalizing the bit line pair, and
wherein a diffusion layer connected with a bit line in the equalizing transistor and a diffusion layer connected with a bit line in the switching transistor are shared.

9. The semiconductor memory according to claim 2 ,
wherein the precharging transistor includes an equalizing transistor for equalizing the bit line pair and a fixed transistor fixed to a precharge potential, and
wherein a diffusion layer connected with the bit line in the equalizing transistor and a diffusion layer connected with a bit line in the fixed transistor are shared.

10. The semiconductor memory according to claim 2 ,
wherein a plurality of the sense amplifiers share the common bus line in common,
wherein a column is selected by selectively turning on the switching transistors of a plurality of the sense amplifiers and connecting one of the plurality of bit line pairs to the common bus line,
wherein column addresses of columns situated on both sides of a column at the boundary of adjacent I/O are identical, and
wherein the gate of switching transistor is formed overriding the boundary of the adjacent I/O.

11. The semiconductor memory according to claim 1 , wherein
the longitudinal direction of the gate of the switching transistor is along a bit line direction.

12. The semiconductor memory according to claim 11 ,
wherein the precharging transistor includes an equalizing transistor for equalizing the bit line pair, and
wherein the diffusion layer is shared for the bit line side of the equalizing transistor and the bit line side of the switching transistor.

13. The semiconductor memory according to claim 11 ,
wherein the precharging transistor includes an equalizing transistor for equalizing the bit line pair and a fixed transistor fixed to a precharge potential, and
wherein the diffusion layer is shared for the bit line side of the equalizing transistor and the bit line side of the fixed transistor.

14. The semiconductor memory according to claim 1 , wherein
the gate voltage of the precharging transistor is at or higher than the gate voltage of the switching transistor.

15. A semiconductor memory comprising:
a memory cell array having a plurality of memory cells;
a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array;
amplifying transistors which are disposed in plurality corresponding to the plurality of bit line pair for amplifying a potential difference between the bit line pair; and
switching transistors selectively connecting the plurality of bit line pairs to a common bus line,
wherein a channel width direction of two or more of the switching transistors sharing the gate is along a longitudinal direction of the gate.

16. The semiconductor memory according to claim 15 ,
wherein the longitudinal direction of the gate is along a vertical direction perpendicular to the bit line direction, and
wherein the switching transistor and the switching transistor of adjacent I/O share the gate at the boundary of adjacent I/O.

Assignees

• Renesas Electronics Corp

Inventors

• Takahashi Hiroyuki

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C2207/005

  Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title