Performing rounding operations responsive to an instruction

Patent metadata

Field	Value
Publication number	US-9286267-B2
Application number	US-201313793648-A
Country	US
Kind code	B2
Filing date	Mar 11, 2013
Priority date	Sep 22, 2006
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a controller to receive a round instruction of an instruction set architecture (ISA) having a format including a source operand, a destination operand and an immediate data element, wherein the controller is to decode the immediate data element to determine if a default round mode is to be overridden based on an override indicator of the immediate data element, and if the default round mode is to be overridden to decode a round mode field of the immediate data element;
an execution unit coupled to the controller to execute a round operation responsive to the round instruction, wherein the execution unit is to execute the round operation according to the round mode field of the immediate data element if the default round mode is to be overridden based on the override indicator; and
a configuration register, wherein when the configuration register is set for denormal numbers as zero and the source operand is a denormal number, the processor is to convert the source operand to zero before execution of the round operation.

2. The processor of claim 1 , wherein the round operation is to round each of a plurality of packed floating point values in the source operand to integer valued floating point values and store each of the plurality of integer valued floating point values in the destination operand.

3. The processor of claim 1 , wherein the controller is to determine if a precision exception is to be suppressed, based on a suppression indicator of the immediate data element.

4. The processor of claim 1 , wherein the execution unit comprises:
a floating point adder to receive a first operand and a second operand; and
a rounder coupled to an output of the floating point adder to perform the round operation.

5. The processor of claim 4 , wherein the controller is to provide control signals to the rounder to perform the round operation.

6. The processor of claim 4 , wherein the floating point adder is to add a first value to the source operand if the source operand is at least equal to a threshold value, otherwise the floating point adder is to subtract the first value from the source operand.

7. The processor of claim 1 , wherein the execution unit is to execute the round operation on at least one element of the source operand to an integer valued floating point value, wherein the source operand comprises a limited precision floating point value.

8. The processor of claim 1 , wherein the execution unit is to execute the round operation on at least one element of the source operand to an integer value, wherein the source operand comprises a floating point value.

9. The processor of claim 1 , wherein the execution unit is to convert the source operand from a signaling not a number to a quiet not a number.

10. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
receiving a user-level rounding instruction of an instruction set architecture (ISA) having a format including a source operand, a destination operand and an immediate value, in a control selector unit of a processor;
determining if a rounding mode override indicator of the immediate value is active by decoding the immediate value in the control selector unit;
if so, obtaining a rounding mode field of the immediate value and dispatching the source operand and information to control a rounding mode to a floating point unit of the processor coupled to the control selector unit; and
executing a rounding operation on the source operand in the floating point unit of the processor responsive to the user-level rounding instruction and according to the information, including if the source operand is a signaling not a number, converting the source operand to a quiet not a number.

11. The non-transitory machine-readable medium of claim 10 , wherein the method further comprises executing the rounding operation responsive to the user-level rounding instruction and according to a rounding mode set forth in a control register of the processor if the rounding mode override indicator of the immediate value is not active.

12. The non-transitory machine-readable medium of claim 10 , wherein the method further comprises maintaining a value of a control register including a default rounding mode during execution of the rounding operation.

13. The non-transitory machine-readable medium of claim 10 , wherein the method further comprises executing the rounding operation according to a round halfway away from zero mode set forth in the immediate value.

14. The non-transitory machine-readable medium of claim 10 , wherein the method further comprises storing a result of the rounding operation in a destination storage area corresponding to the destination operand as an integer valued floating point value, wherein the source operand comprises a limited precision floating point value.

15. The non-transitory machine-readable medium of claim 10 , wherein the method further comprises suppressing a precision exception that results from the rounding operation if a precision suppression indicator of the immediate value is active.

16. The non-transitory machine-readable medium of claim 10 , wherein the user-level rounding instruction comprises an instruction of the instruction set architecture to perform the rounding operation on a plurality of single instruction multiple data (SIMD) elements of the source operand.

17. A system comprising:
a processor comprising:
an execution unit to execute a round instruction on a first operand to obtain a rounded result in accordance with a round mode portion of a control field associated with the round instruction if an override indicator separate from the round mode portion is present in the control field;
a selector unit coupled to the execution unit to receive the round instruction and the control field, wherein the selector unit is to decode the round mode portion of the control field and generate control signals therefrom if the override indicator is present and to provide the control signals to the execution unit to cause execution of the round instruction, wherein when the first operand is a signaling not a number, the execution unit is to convert the first operand from the signaling not a number to a quiet not a number, the round mode portion to encode one of a plurality of round modes; and
a register to store a default round mode for the execution unit and to store status information regarding execution in the execution unit, wherein the execution unit is to execute the round instruction in accordance with a different round mode than the default round mode if the override indicator is present in the control field, and to not update the status information indicative of a precision exception caused by execution of the round instruction if a suppression indicator is present in the control field; and

a dynamic random access memory (DRAM) coupled to the processor.

18. The system of claim 17 , wherein the execution unit comprises a floating point unit to perform a round operation on the first operand responsive to the control signals from the selector unit, wherein the first operand comprises a limited precision value.

19. The system of claim 17 , wherein the execution unit is to perform the different round mode via addition of a first value to the first operand if the first operand is less than or equal to a threshold value, otherwise via addition of a second value to the first operand, wherein the first value comprises a negat

Assignees

• Intel Corp

Inventors

• Zohar Ronen
• Story Shane

Classifications

• G06F9/30167

  of immediate specifier, e.g. constants · CPC title

• G06F9/30014 Primary

  with variable precision · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/30181

  Instruction operation extension or modification · CPC title