Semiconductor devices with impedance matching-circuits

Patent metadata

Field	Value
Publication number	US-9281283-B2
Application number	US-201213611793-A
Country	US
Kind code	B2
Filing date	Sep 12, 2012
Priority date	Sep 12, 2012
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

Embodiments of semiconductor devices (e.g., RF devices) include a substrate, an isolation structure, an active device, a lead, and a circuit. The isolation structure is coupled to the substrate, and includes an opening. An active device area is defined by a portion of the substrate surface that is exposed through the opening. The active device is coupled to the substrate surface within the active device area. The circuit is electrically coupled between the active device and the lead. The circuit includes one or more elements positioned outside the active device area (e.g., physically coupled to the isolation structure and/or under the lead). The elements positioned outside the active device area may include elements of an envelope termination circuit and/or an impedance matching circuit. Embodiments also include method of manufacturing such semiconductor devices.

First claim

What is claimed is:

1. A device comprising:
a substrate having a surface;
an isolation structure having a top surface and a bottom surface coupled to the surface of the substrate, wherein the isolation structure includes an opening, and an active device area is defined by a portion of the surface of the substrate that is exposed through the opening;
an active device coupled to the surface of the substrate within the active device area;
a lead coupled to the isolation structure; and
an output circuit electrically coupled between the active device and the lead, wherein the output circuit includes a plurality of elements, wherein one or more elements of the plurality of elements is positioned outside the active device area, wherein the one or more elements positioned outside the active device area include elements of an envelope frequency termination circuit, and wherein the one or more elements positioned outside the active device area are directly physically coupled to the isolation structure.

2. The device of claim 1 , wherein the output circuit comprises:
a first inductive element coupled between the active device and the lead;
a shunt circuit coupled between the active device and the substrate; and
the envelope termination circuit coupled between the shunt circuit and the substrate, wherein the one or more elements positioned outside the active device area comprise one or more elements of the envelope termination circuit.

3. A device comprising:
a substrate having a surface;
an isolation structure having a top surface and a bottom surface coupled to the surface of the substrate, wherein the isolation structure includes an opening, and an active device area is defined by a portion of the surface of the substrate that is exposed through the opening;
an active device coupled to the surface of the substrate within the active device area;
a lead coupled to the isolation structure; and
an output circuit electrically coupled between the active device and the lead, wherein the output circuit includes a plurality of elements, wherein one or more elements of the plurality of elements is positioned outside the active device area, wherein the one or more elements positioned outside the active device area include elements of an envelope frequency termination circuit, wherein the one or more elements positioned outside the active device area are physically coupled to the isolation structure, and wherein the output circuit comprises:
a first inductive element comprising a plurality of bondwires coupled between the active device and the lead;
a shunt circuit coupled between the active device and the substrate, wherein the shunt circuit comprises a first capacitor and a second inductive element coupled in series, wherein the first capacitor is coupled to the surface of the substrate within the active device area, and the second inductive element comprises a plurality of bondwires coupled between the active device and the first capacitor;
the envelope termination circuit coupled between the shunt circuit and the substrate, wherein the envelope termination circuit comprises a third inductive element, a resistor, and a second capacitor coupled in series, wherein the third inductive element comprises a plurality of bondwires coupled between the first capacitor and the resistor; and
a low-pass matching circuit coupled between the lead and the substrate, wherein the low-pass matching circuit comprises a third capacitor coupled between the lead and the substrate,
and wherein the one or more elements positioned outside the active device area is selected from the third inductive element, the resistor, the second capacitor, and the third capacitor.

4. The device of claim 1 , wherein the isolation structure comprises inorganic materials.

5. The device of claim 1 , wherein the isolation structure comprises organic materials.

6. A device comprising:
a substrate having a conductive surface;
an isolation structure having a top surface and a bottom surface coupled to the conductive surface of the substrate, wherein the isolation structure includes an opening, and an active device area is defined by a portion of the conductive surface of the substrate that is exposed through the opening;
a transistor coupled to the conductive surface of the substrate within the active device area;
a first lead coupled to the isolation structure; and
an output circuit electrically coupled between the transistor and the first lead, wherein the output circuit includes a plurality of elements, wherein one or more elements of the plurality of elements is positioned outside the active device area, wherein the one or more elements positioned outside the active device area include elements of an envelope frequency termination circuit, and wherein the one or more elements positioned outside the active device area are directly physically coupled to the isolation structure.

7. The device of claim 6 , wherein the first lead is an output lead, and the output circuit is coupled between a current conducting terminal of the transistor and the output lead.

8. A device comprising:
a substrate having a conductive surface;
an isolation structure having a top surface and a bottom surface coupled to the conductive surface of the substrate, wherein the isolation structure includes an opening, and an active device area is defined by a portion of the conductive surface of the substrate that is exposed through the opening;
a transistor coupled to the conductive surface of the substrate within the active device area:
an output lead coupled to the isolation structure; and
an output circuit electrically coupled between a current conducting terminal of the transistor and the output lead, wherein the output circuit includes a plurality of elements, wherein one or more elements of the plurality of elements is positioned outside the active device area, wherein the one or more elements positioned outside the active device area include elements of an envelope frequency termination circuit, wherein the one or more elements positioned outside the active device area are physically coupled to the isolation structure, wherein the one or more elements positioned outside the active device area include a resistor positioned on a top surface of the isolation structure, and a capacitor integrally formed with the isolation structure, and wherein the resistor is chosen from a thick film resistor, a thin film resistor, and a discrete resistor;
a first conductive pad on the top surface of the isolation structure, wherein the first conductive pad is electrically coupled to the current conducting terminal of the transistor, and a first terminal of the resistor is coupled to the first conductive pad; and
a second conductive pad on the top surface of the isolation structure, wherein a second terminal of the resistor and a first terminal of the capacitor are coupled to the second conductive pad, and a second terminal of the capacitor is coupled to the conductive surface of the substrate.

9. The device of claim 8 , further comprising:
one or more conductive structures in or on the isolation structure, which electrically couples the second terminal of the capacitor to the conductive surface of the substrate, wherein the one or more conductive structures is selected from one or more vias, one or more castellations, and edge plating.

10. The device of claim 7 , wherein:
the one or more elements positioned outside the active device area include a resistor and a discrete capacitor positioned on a top surface of the isolation structure, wherein the resistor is chosen from a thick film resistor, a thin film resistor, and a discrete resistor, and
the device further comprises:
a first condu

Assignees

• Viswanathan Lakshminarayan
• Jones Jeffrey K
• Marshall Scott D
• Freescale Semiconductor Inc

Inventors

• Viswanathan Lakshminarayan
• Jones Jeffrey K
• Marshall Scott D

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07553

  changes in shapes · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title