Information processing device including memory management device managing access from processor to memory and memory management method

Patent metadata

Field	Value
Publication number	US-9280466-B2
Application number	US-55595209-A
Country	US
Kind code	B2
Filing date	Sep 9, 2009
Priority date	Sep 9, 2008
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

First claim

What is claimed is:

1. An information processing device including a memory management device, comprising:
a processor;
a volatile memory;
a non-volatile memory;
an accepter which accepts write-target-data from the processor;
a storage which holds a coloring level; and
an operating system which generates an access frequency of the write-target-data and an importance of the write-target-data,
wherein the operating system:
calculates the coloring level based on the access frequency of the write-target-data and the importance of the write-target-data,
obtains a threshold value for selecting the volatile memory or the non-volatile memory,
wherein the threshold value is determined based on a remaining capacity of a usable area in the volatile memory and the non-volatile memory, and
determines whether to write the write-target-data in the volatile memory or the non-volatile memory by comparing the coloring level and the threshold value.

2. The information processing device according to claim 1 , wherein the importance is determined using static information.

3. The information processing device according to claim 2 , wherein the access frequency is determined based on static information and dynamic information.

4. The information processing device according to claim 1 , wherein the volatile memory and non-volatile memory comprise different areas of a memory addressable by the operating system.

5. An information processing device including a memory management device, comprising:
a processor;
a volatile memory;
a non-volatile memory;
an accepting section which accepts write-target-data from the processor;
a storage which holds a coloring level; and
an operating system which generates an access frequency of write-target-date and importance of the write-target-data, wherein the operating system:
calculates the coloring level based on the access frequency of the write-target-data and the importance of the write-target-data, where coloring level =min, (importance×W+access frequency ×(1−W))), W is the correction value for weighting the importance and the access frequency, 0≦W≦1, the importance is min(9, max(static importance, importance designated by user), 0≦static importance≦9, the access frequency=static access frequency ×T, the static access frequency=max(access frequency designated by the user, access frequency designated by the operating system), T=max(0,(−access time interval/maximum access time interval)+1), and 0≦T≦1,
obtains a threshold value for selecting the volatile memory or the non-volatile memory wherein the threshold value is determined based on a remaining capacity of a usable area in the volatile memory and the non-volatile memory, and
determines whether to write the write-target data in the volatile memory or the non-volatile memory by comparing the coloring level and the threshold value.

6. A new method for managing memory on an information processing device, comprising:
receiving write-target-data from a processor of the information processing device;
at an operating system executing on the information device:
obtaining an access frequency and an importance of the write-target-data;
calculating a coloring level for the write-target-data based on the access frequency of the write-target-data and the importance of the write-target-data;
storing the coloring level for the write-target-data;
determining a threshold value based on a remaining capacity of a usable area in a volatile memory and a non-volatile memory of the information processing device; and
determining whether to write the write-target-data in the volatile memory or the non-volatile memory by comparing the coloring level and the threshold value.

7. The method according to claim 6 , wherein the importance is determined using static information.

8. The method according to claim 7 , wherein the access frequency is determined based on static information and dynamic information.

9. The method according to claim 6 , wherein the volatile memory and non-volatile memory comprise different areas of a memory addressable by the operating system.

Assignees

• Kunimatsu Atsushi
• Nakai Hiroto
• Sakamoto Hiroyuki
• Maeda Kenichi
• Miyagawa Masaki
• Nozue Hiroshi
• Kawagome Kazuhiro
• Toshiba Kk

Inventors

• Kunimatsu Atsushi
• Nakai Hiroto
• Sakamoto Hiroyuki
• Maeda Kenichi
• Miyagawa Masaki
• Nozue Hiroshi
• Kawagome Kazuhiro

Classifications

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F2212/1036

  Life time enhancement · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0804 Primary

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F2212/2022

  Flash memory · CPC title