Decode time instruction optimization for load reserve and store conditional sequences

Patent metadata

Field	Value
Publication number	US-9280349-B2
Application number	US-201313783985-A
Country	US
Kind code	B2
Filing date	Mar 4, 2013
Priority date	Mar 28, 2012
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

A technique is provided for replacing an atomic sequence. A processing circuit receives the atomic sequence. The processing circuit detects the atomic sequence. The processing circuit generates an internal atomic operation to replace the atomic sequence.

First claim

What is claimed is:

1. A computer implemented method for replacing an atomic sequence, the method comprising:
receiving, by a processing circuit, the atomic sequence;
detecting, by the processing circuit, the atomic sequence; and
generating, by the processing circuit, an internal atomic operation to replace the atomic sequence;
based on separate instructions of the atomic sequence not being a same group and based on the separate instructions being positioned to execute separately, configuring an instruction decoder to perform instruction cache marking of the separate instructions that are not in the same group to force a load reserve instruction and a store conditional instruction into the same group;
configuring the instruction decoder to initially mark the load reserve instruction based on the load reserve instruction being detected first in the separate instructions or initially mark the store conditional instruction based on the store conditional instruction being detected first in the separate instructions;
configuring the instruction decoder to complete formation of the same group by marking the load reserve instruction based on the load reserve instruction being detected last in the separate instructions or by marking the store conditional instruction based on the store conditional instruction being detected last in the separate instructions; and
configuring the instruction decode to translate the separate instructions having been grouped into the same group for the atomic sequence into the internal atomic operation.

2. The computer implemented method of claim 1 , further comprising executing the internal atomic operation in place of the atomic sequence.

3. The computer implemented method of claim 1 , wherein the atomic sequence comprises a load reserve instruction and a store conditional instruction.

4. The computer implemented method of claim 3 , wherein detecting the atomic sequence comprises recognizing the load reserve instruction and the store conditional instruction to detect the atomic sequence that needs to be replaced.

5. The computer implemented method of claim 1 , wherein a predecode optimizer is configured to detect the atomic sequence and generate the internal atomic operation prior to caching by an instruction cache.

6. The computer implemented method of claim 1 , wherein the internal atomic operation is executed in at least one of a memory subsystem and an atomic function unit.

Assignees

• IBM

Inventors

• Gshwind Michael K

Classifications

• G06F9/30196 Primary

  using decoder, e.g. decoder per instruction set, adaptable or programmable decoders · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F9/3844

  using dynamic branch prediction, e.g. using branch history tables · CPC title

• G06F9/30087

  Synchronisation or serialisation instructions · CPC title