Bead for 2.5D/3D chip packaging application

Patent metadata

Field	Value
Publication number	US-9275950-B2
Application number	US-201213481974-A
Country	US
Kind code	B2
Filing date	May 29, 2012
Priority date	May 29, 2012
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

An integrated circuit package having a multilayer interposer has one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads has a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer, and two terminal end segments connected to the power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters.

First claim

What is claimed is:

1. An integrated circuit package comprising:
a multilayer interposer having one or more integrated devices mounted thereon, the interposer comprising multiple layers of wiring structures; and
one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads comprising:
a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer; and
two terminal end segments connected to power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters,

wherein the convoluted wiring pattern further comprises a plurality of vias, provided in a via layer between each of the multiple layers of wiring structures, establishing electrical connection between the layers of wiring structures.

2. The integrated circuit package of claim 1 , wherein the convoluted wiring pattern comprises a serpentine-like portion between the two terminal end segments.

3. The integrated circuit package of claim 1 , wherein the convoluted wiring pattern comprises a meandering loop portion between the two terminal end segments.

4. The integrated circuit package of claim 1 , wherein the plurality of vias in the via layer between the first and second wiring layers connecting the first set of the plurality of line segments and the second set of the plurality of line segments extend at least 100 μm along a X or Y direction within the via layer, thereby forming a serpentine-like convoluted pattern and comprising a substantial portion of the total length of the metal wiring bead.

5. The integrated circuit package of claim 4 , wherein the plurality of vias comprise at least 50% of the total length of the metal wiring bead.

6. The integrated circuit package of claim 1 , wherein the convoluted wiring pattern comprises a first convoluted wiring pattern formed in the first of the multiple layers of wiring structures;
a second convoluted wiring pattern formed in the second of the multiple layers of wiring structures;
a third convoluted wiring pattern formed in the third of the multiple layers of wiring structures; and
wherein the three convoluted wiring patterns are electrically connected in series by the plurality of vias;
wherein the three convoluted wiring patterns have different size outlines, the first convoluted wiring pattern having the smallest outline, the third convoluted wiring pattern having the largest outline, thereby the first and second convoluted wiring pattern are nested within the outline of the third convoluted wiring pattern.

7. The integrated circuit package of claim 6 , wherein a first via provided in a via layer between the first of the multiple layers of wiring structures and the second of the multiple layers of wiring structures establish the electrical connection between the first and second convoluted wiring patterns; and
a second via provided in a via layer between the second of the multiple layers of wiring structures and the third of the multiple layers of wiring structures, establish the electrical connections between the second and third convoluted wiring patterns.

8. The integrated circuit package of claim 1 ,
wherein the convoluted wiring pattern comprises a first set of a plurality of line segments provided in said one of the multiple layers of wiring structures; and the integrated circuit package further comprising a second convoluted wiring pattern formed in a second one of the multiple layers of wiring structures in the interposer,
wherein the second convoluted wiring pattern comprises a second set of a plurality of line segments provided in a second of the multiple layers of wiring structures, wherein the first set of the plurality of line segments and the second set of the plurality of line segments are in a staggered arrangement; and
the plurality of vias in the via layer between the first and second layers of wiring structures connecting the first set of the plurality of line segments and the second set of the plurality of line segments.

9. The integrated circuit package of claim 8 , wherein the plurality of vias in the via layer between the first and second wiring layers connecting the first set of the plurality of line segments and the second set of the plurality of line segments extend at least 100 μm along a X or Y direction within the via layer, thereby forming a serpentine-like convoluted pattern and comprising a substantial portion of the total length of the metal wiring bead.

10. The integrated circuit package of claim 9 , wherein the plurality of vias comprise at least 50% of the total length of the metal wiring bead.

11. The integrated circuit package of claim 8 , wherein the convoluted wiring patterns comprise a serpentine-like portion between the two terminal end segments.

12. The integrated circuit package of claim 8 , wherein the convoluted wiring patterns comprise a meandering loop portion between the two terminal end segments.

13. An integrated circuit package comprising:
a multilayer interposer having one or more integrated devices mounted thereon, the interposer comprising multiple layers of wiring structures; and
one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads comprising:
a convoluted wiring pattern formed in each of at least three of the multiple layers of wiring structures in the interposer; and
two terminal end segments connected to power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters,

wherein the convoluted wiring pattern formed in the first of the at least three of the multiple layers of wiring structures comprises a first serpentine-like segment;
the convoluted wiring pattern formed in the second of the at least three of the multiple layers of wiring structures comprises a second serpentine-like segment;
the convoluted wiring pattern formed in the third of the at least three of the multiple layers of wiring structures comprises a third serpentine-like segment; and
wherein the three serpentine-like segments are electrically connected in series.

14. The integrated circuit package of claim 13 , wherein the first and second serpentine-like segments are connected by a via provided in the via layer between the first and second of the multiple layers of wiring structures, and the second and third serpentine-like segments are connected by a via provided in the via layer between the first and second of the multiple layers of wiring structures.

15. An integrated circuit package comprising:
a multilayer interposer having one or more integrated devices mounted thereon, the interposer comprising multiple layers of wiring structures; and
one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads comprising:
a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer; and
two terminal end segments connected to power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters,

wherein the convoluted wiring pattern comprises two convoluted segments formed in one of the multiple layers of wiring structures in the interposer and the two convoluted segments are electrically connected in series by a connecting segment formed in a second one of the multiple layers of wiring structures in the interposer, wherein vias, provided in a via layer between the one of the multiple layers of wiring structures and the second one of the multiple layers of wiring structures, establish the

Assignees

• Kuo Feng Wei
• Chen Huan-Neng
• Jou Chewn-Pu
• Yeh Der-Chyang
• Wang Chuei-Tang
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Feng Wei
• Chen Huan-Neng
• Jou Chewn-Pu
• Yeh Der-Chyang
• Wang Chuei-Tang

Classifications

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W44/209

  Vertical interconnections, e.g. vias · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title