Method for making a lithography mask

Patent metadata

Field	Value
Publication number	US-9274414-B2
Application number	US-201414558842-A
Country	US
Kind code	B2
Filing date	Dec 3, 2014
Priority date	Nov 1, 2012
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.

First claim

What is claimed is:

1. A method of making a mask, the method comprising:
receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature;
modifying the IC design layout by adjusting a dimension of the first feature based on the first distance; and
generating a tape-out data from the modified IC design layout for mask making.

2. The method of claim 1 , further comprising applying a logic operation (LOP) to the IC design layout.

3. The method of claim 2 , wherein, the applying of the LOP includes
identifying the first feature vertically overlying the second feature; and
determining an adjustment to the dimension of the first feature.

4. The method of claim 3 , wherein
the adjustment is a function of the first distance; and
the adjusting of the dimension of the first includes adding the adjustment to the dimension of the first feature.

5. The method of claim 3 , wherein the adjustment is a non-zero value if the first distance is larger than a first predetermined value.

6. The method of claim 3 , wherein the adjustment is zero if the dimension is larger than a second predetermined value.

7. The method of claim 3 , wherein the adjustment is zero if a second distance between the first feature and an adjacent feature in the first pattern layer is less than a third predetermined value.

8. A method of making a mask, the method comprising:
receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein when the first and second features are positioned such that, when formed in a substrate, the first and second features are spaced a first distance between each other;
modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, wherein the dimension of the first feature is adjusted by adding a value when the first distance is larger than a first predetermined value; and
generating a mask for the first pattern layer, including the modified first feature.

9. The method of claim 8 , wherein the value is a function of the first predetermined value.

10. A method of making a mask, the method comprising:
receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein when the first and second features are positioned such that, when formed in a substrate, the first and second features are spaced a first distance between each other;
performing a logic operation (LOP) to the IC design layout, such that the LOP biases the first feature based on the first distance; and
generating a tape-out data from the modified IC design layout for mask making.

11. The method of claim 10 , wherein the LOP is determined by a fabrication facility that will use the mask and wherein the LOP includes the second feature of the second pattern layer.

12. The method of claim 10 , wherein, the applying of the LOP includes
identifying the first feature vertically overlying the second feature; and
determining an adjustment to the dimension of the first feature.

13. The method of claim 12 , wherein
the adjustment is a function of the first distance; and
the adjusting of the dimension of the first includes adding the adjustment to the dimension of the first feature.

14. The method of claim 12 , wherein the adjustment is a non-zero value if the first distance is larger than a first predetermined value.

15. The method of claim 12 , wherein the adjustment is zero if the dimension is larger than a second predetermined value.

16. The method of claim 12 , wherein the adjustment is zero if a second distance between the first feature and an adjacent feature in the first pattern layer is less than a third predetermined value.

17. The method of claim 12 , wherein the adjustment is determined by an equation X=X 0 +2D, wherein X 0 is the originally designed dimension of the second feature and D is a fourth predetermined value.

18. The method of claim 17 , wherein if the designed dimension X of the second feature is larger than a first predetermined value, or the distance between the two adjacent second features is smaller than a second predetermined value, the fourth predetermined value D is zero.

19. The method of claim 17 , wherein if the designed dimension X of the second feature is smaller than a first predetermined value, the distance between the two adjacent second features is larger than a second predetermined value, and a distance between a first edge of the first feature and a second edge of the second feature is smaller than a third predetermined value, the fourth predetermined value D is zero.

20. The method of claim 17 , wherein if the designed dimension X of the second feature is smaller than a first predetermined value, the distance between the two adjacent second features is larger than a second predetermined value, and a distance Y between an edge of the first feature and an edge of the second feature is larger than a third predetermined value, the fourth predetermined value D a non-zero value, and is a function of the distance Y.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Liu Yu-Lun
• Liu Chia-Chu
• Chen Kuei-Shun
• Wang Chung-Ming
• Lin Chie-Chieh

Classifications

• G03F1/00

  Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof · CPC title

• G03F1/38 Primary

  Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof · CPC title

• G03F7/70433 Primary

  Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors · CPC title