Method and apparatus for testing a device-under-test

Patent metadata

Field	Value
Publication number	US-9274175-B2
Application number	US-201013574573-A
Country	US
Kind code	B2
Filing date	Jan 20, 2010
Priority date	Jan 20, 2010
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A method for testing a device-under-test includes receiving, from at least one test channel circuit dedicated to communicate with an input/output pin of the device-under-test by means of at least one hardware resource, at least one logical control command describing a desired operation of the at least one hardware resource, and converting, by means of a resource controller, the at least one logical control command into at least one dedicated control command for the at least one hardware resource, wherein the at least one dedicated control command is adapted to be received by a physical implementation of the at least one hardware resource.

First claim

What is claimed is:

1. An apparatus for testing a device, the apparatus comprising:
a test channel circuit operable to communicate with an input/output pin of the device using a hardware resource; and
a resource controller coupled to the test channel circuit and configured to receive a logical control command describing a requested operation of the hardware resource, wherein the resource controller is configured to convert the logical control command into a dedicated control command for the hardware resource, and wherein further the dedicated control command is configured to be received by a physical implementation of the hardware resource.

2. The apparatus according to claim 1 , wherein the logical control command is generated by the test channel circuit and is independent from the physical implementation of the hardware resource.

3. The apparatus according to claim 1 , wherein the test channel circuit comprises:
a digital test pattern generator configured for generating a digital test pattern; and
a time formatter configured for associating a timing to binary values of the digital test pattern.

4. The apparatus according to claim 1 , wherein the test channel circuit comprises:
a digital test pattern comparator configured for comparing a test pattern received from the input/output pin with an expected digital test pattern.

5. The apparatus according to claim 1 , wherein the hardware resource is disposed external to the test channel circuit, and wherein further the hardware resource is configured to couple the test channel circuit to the device.

6. The apparatus according to claim 1 , wherein the hardware resource is operable to convert a signal or a test pattern to or from the device into a signal suited for one of the input/output pin and the test channel circuit.

7. The apparatus according to claim 1 further comprising:
a plurality of test channel circuits, wherein the resource controller is shared by the plurality of test channel circuits and is configured to multiplex different logical control commands from different test channel circuits to a single control data port which is coupled to a multi-channel port of a multi-channel hardware resource.

8. The apparatus according to claim 1 further comprising:
a plurality of test channel circuits, wherein the resource controller is adapted to temporally schedule different logical control commands from different test channel circuits, and wherein the different test channel circuits are configured to subsequently access a single hardware resource in a time division multiplexing scheme.

9. The apparatus according to claim 1 , wherein the resource controller is re-configurable for adapting the resource controller to a physical implementation of a physically connected hardware resource.

10. A non-transitory computer-readable medium having computer-readable program code embodied therein for causing a computer system to perform a method of testing, said method comprising:
receiving a logical control command from a test channel circuit dedicated to communicate with an input/output pin of a device under test using a hardware resource, wherein the logical control command describes a requested operation of the hardware resource; and
converting the logical control command into a dedicated control command for the hardware resource, wherein the dedicated control command is configured to be received by a physical implementation of the hardware resource.

11. The computer-readable medium of claim 10 , wherein the logical control command is generated by the test channel circuit and is independent from the physical implementation of the hardware resource.

12. The computer-readable medium of claim 10 , wherein the hardware resource is disposed external to the test channel circuit, and wherein further the hardware resource is configured to connect the test channel circuit to the device.

13. The computer-readable medium of claim 10 , wherein the hardware resource is configured to convert a signal or a test pattern to or from the device into a signal suited for one of the input/output pin and the test channel circuit.

14. The computer-readable medium of claim 10 , wherein the method further comprises:
receiving a plurality of logical control commands from a plurality of test channel circuits;
sharing the resource controller by the plurality of test channel circuits; and
multiplexing different logical control commands from different test channel circuits to a single control data port which is coupled to a multi-channel port of a multi-channel hardware resource.

15. The computer-readable medium of claim 10 , wherein the method further comprises:
receiving a plurality of logical control commands from a plurality of test channel circuits; and
scheduling, using the resource controller, different logical control commands from different test channel circuits, and wherein the different test channel circuits subsequently access a single hardware resource in a time division multiplexing scheme.

16. The computer-readable medium of claim 10 , wherein the resource controller is re-configurable for adapting the resource controller to a physical implementation of a physically connected hardware resource.

17. A system comprising a processor and a memory, wherein the memory comprises instructions that when executed by the processor implement a method of testing, the method comprising:
receiving, from a test channel circuit dedicated to communicate with an input/output pin of the device using a hardware resource, wherein a logical control command describes a desired operation of the hardware resource; and
converting the logical control command into a dedicated control command for the hardware resource, wherein the dedicated control command is configured to be received by a physical implementation of the hardware resource.

Assignees

• Golov Gil
• Henkel Thomas
• Larson Ronald
• Knoch Ulrich
• Advantest Corp

Inventors

• Golov Gil
• Henkel Thomas
• Larson Ronald
• Knoch Ulrich

Classifications

• G01R31/31907 Primary

  Modular tester, e.g. controlling and coordinating instruments in a bus based architecture · CPC title

• G01R31/319 Primary

  Tester hardware, i.e. output processing circuits · CPC title