Semiconductor device with active shielding of leads

Patent metadata

Field	Value
Publication number	US-9271390-B2
Application number	US-201414332372-A
Country	US
Kind code	B2
Filing date	Jul 15, 2014
Priority date	Jul 15, 2014
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A semiconductor device has a multi-wire lead and a die having a multi-site bond pad. A shielding wire and a guarded wire both extend from the multi-wire lead to the multi-site bond pad. The shielding wire (or wires) provide active shielding to the guarded wire by simultaneously transmitting the same signal as the guarded wire between the multi-wire lead the multi-site bond pad.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a die having a multi-site bond pad;
a multi-wire lead;
at least one shielding wire extending from the multi-wire lead to the multi-site bond pad; and
a guarded wire extending from the multi-wire lead to the multi-site bond pad, wherein the at least one shielding wire and the guarded wire simultaneously transmit the same signals between the multi-site bond pad and the multi-wire lead.

2. The semiconductor device of claim 1 , wherein the multi-wire lead is “T” shaped.

3. The semiconductor device of claim 2 , wherein the at least one shielding wire comprises two shielding wires extending from the multi-wire lead to the multi-site bond pad.

4. The semiconductor device of claim 3 , wherein the two shielding wires extend between the multi-wire lead and the multi-site bond pad on opposite sides of the guarded wire.

5. The semiconductor device of claim 1 , wherein the multi-site bond pad has at least one shielding-wire bond-pad site and a guarded-wire bond-pad site.

6. The semiconductor device of claim 5 , wherein the multi-site bond pad has two shielding-wire bond-pad sites each located on opposite sides of the guarded-wire bond-pad site.

7. The semiconductor device of claim 5 , wherein the at least one shielding-wire bond-pad site and the guarded-wire bond-pad site are physically connected to one another without having impedance therebetween.

8. The semiconductor device of claim 1 , wherein the semiconductor device is a low-profile quad flat package.

9. The semiconductor device of claim 1 , wherein the signals are neither power nor ground voltage.

10. The semiconductor device of claim 1 , wherein the multi-site bond pad comprises at least one shielding-wire sub-bond-pad that has the shielding wire bonded thereto, and a guarded-wire sub-bond-pad that has the guarded wire bonded thereto, wherein the shielding-wire sub-bond-pad and the guarded-wire sub-bond-pad are physically connected to one another without having impedance therebetween.

11. The semiconductor device of claim 10 , wherein the at least one shielding-wire sub-bond-pad comprises two shielding-wire sub-bond-pads respectively located on opposite sides of the guarded-wire sub-bond-pad, and wherein the at least one shielding wire comprises two shielding wires respectively extending from the multi-wire lead to the two shielding-wire sub-bond-pads such that the two shielding wires are generally parallel to and on opposing sides of the guarded wire.

Assignees

• Srivastava Sunaina
• Imam Raza
• Kansal Gagan
• Varshney Sumit
• Freescale Semiconductor Inc

Inventors

• Srivastava Sunaina
• Imam Raza
• Kansal Gagan
• Varshney Sumit

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title