Time-to-digital converter based on a voltage controlled oscillator

Patent metadata

Field	Value
Publication number	US-9270288-B2
Application number	US-201414448482-A
Country	US
Kind code	B2
Filing date	Jul 31, 2014
Priority date	Nov 27, 2013
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A phase-locked loop (PLL) includes a time to voltage converter to convert a phase error between a reference signal and a feedback signal of the PLL to one or more voltage signals. An oscillator-based analog to digital converter (ADC) receives the one or more voltage signals and controls one or more oscillators according to the voltages. The oscillator-based ADC determines a digital value corresponding to the phase error based on the frequencies of the one or more oscillators.

First claim

What is claimed is:

1. A phase-locked loop (PLL) comprising:
a time to voltage converter to convert a phase error corresponding to a time difference between a reference signal and a feedback signal of the PLL to one or more voltage signals; and
an oscillator-based analog to digital converter (ADC) coupled to receive the one or more voltage signals and convert the one or more voltage signals to a digital value corresponding to the phase error, the oscillator-based ADC having one or more oscillators having respective frequencies responsive to the one or more voltage signals.

2. The PLL as recited in claim 1 wherein the oscillator-based ADC comprises:
a first ring oscillator and first tuning transistors coupling stages of the first ring oscillator to a first supply node and second tuning transistors coupling the stages of the first ring oscillator to a second supply node.

3. The PLL as recited in claim 2 wherein the one or more voltage signals is one voltage and the apparatus further comprises:
a first transistor having a first current carrying node coupled to the first supply node and a second current carrying node coupled to a gate of the first transistor;
a second transistor having a third current carrying node coupled to the second current carrying node, a fourth current carrying node coupled to the second supply node, and a gate of the second transistor coupled to the one voltage;
wherein respective gates of the second tuning transistors are coupled to the one voltage and respective gates of the first tuning transistors are coupled to the second current carrying node of the first transistor.

4. The PLL as recited in claim 2 wherein oscillator-based ADC further comprises:
a second ring oscillator and third tuning transistors coupling stages of the second ring oscillator to the first supply node and fourth tuning transistors coupling the stages of the second ring oscillator to the second supply node.

5. The PLL as recited in claim 4 wherein the time to voltage converter comprises:
a phase detector coupled to supply a charge control signal corresponding to the phase error;
a first resistor-based charge pump circuit to generate a first voltage signal according to the charge control signal as one of the voltage signals; and
a second resistor-based charge pump circuit to generate a second voltage signal according to the charge control signal as another of the voltage signals.

6. The PLL as recited in claim 5 wherein,
the first voltage signal corresponds to a positive representation of the phase error; and wherein
the second voltage signal corresponds to a negative representation of the phase error.

7. The PLL as recited in claim 6 wherein the first voltage signal is supplied to the second and third tuning transistors and wherein the second voltage signal is supplied to the first and fourth tuning transistors.

8. The PLL as recited in claim 4 wherein the first and third tuning transistors are PMOS and the second and fourth tuning transistors are NMOS.

9. The PLL as recited in claim 4 wherein the oscillator-based ADC further comprises:
a first transition counter to count first transitions in the first ring oscillator and to supply a first digital value corresponding to the phase error based on the first transitions; and
a second transition counter to count second transitions in the second ring oscillator and to supply a second digital value corresponding to the phase error based on the second transitions.

10. The PLL as recited in claim 9 further comprising a circuit to combine the first and second digital values to generate the digital value of the oscillator-based ADC.

11. The PLL as recited in claim 9 further comprising a coarse phase detector circuit to provide one or more detection signals when the phase error is outside of a desired operating range.

12. The PLL as recited in claim 11 further comprising a frequency error detector.

13. A method of operating a phase-locked loop (PLL) comprising:
converting a phase error corresponding to a time difference between a reference signal and a feedback signal of the PLL to one or more voltage signals; and
controlling a frequency of an oscillator in an oscillator-based analog to digital converter according to the one or more voltage signals;
determining a digital value corresponding to the phase error based on the frequency.

14. The method as recited in claim 13 further comprising:
generating a first voltage corresponding to the phase error as one of the one or more voltage signals.

15. The method as recited in claim 14 further comprising:
supplying the first voltage to the oscillator of the oscillator-based ADC, the oscillator being a first ring oscillator; and
tuning a frequency of the first ring oscillator using the first voltage.

16. The method as recited in claim 15 further comprising:
counting transitions of the first ring oscillator to determine a first digital value corresponding to the phase difference.

17. The method as recited in claim 14 further comprising:
generating a second voltage corresponding to the phase error,
wherein the first voltage corresponds to a positive representation of the phase error and the second voltage corresponds to a negative representation of the phase error.

18. The method as recited in claim 17 further comprising:
supplying the first voltage to a first ring oscillator; and
supplying the second voltage to a second ring oscillator.

19. The method as recited in claim 17 further comprising supplying the first voltage and the second voltage to tune a first ring oscillator, a frequency of the first ring oscillator being based on the first and second voltages.

20. The method as recited in claim 19 further comprising:
supplying the first and second voltages to tune a second ring oscillator of the oscillator-based ADC;
counting transitions of the first ring oscillator to determine a first digital value corresponding to the phase difference; and
counting transitions of the second ring oscillator to determine a second digital value corresponding to the phase error.

21. The method as recited in claim 20 further comprising combining the first digital value and the second digital value to generate the digital value of the oscillator-based ADC.

22. The method as recited in claim 13 further comprising detecting when a phase error signal is outside of a steady-state operating range and augmenting the phase error signal based on the detecting.

23. The PLL as recited in claim 22 further comprising detecting a frequency error in the phase-locked loop and augmenting the phase error signal in response to a detected frequency error.

24. A method of operating a phase-locked loop (PLL) comprising:
converting a phase error corresponding to a time difference between a reference signal and a feedback signal of the PLL to a first voltage signal corresponding to a positive representation of the phase error in a first charge pump;
converting the phase error to a second voltage signal corresponding to a negative representation of the phase error in a second charge pump;
supplying the first voltage signal and the second voltage signal to tune a first ring oscillator to thereby control a frequency of the first ring oscillator and supplying the first voltage signal and the second voltage signal to tune a second ring oscillator to thereby control a frequency of the second ring oscillator; and
determining a digital value cor

Assignees

• Silicon Lab Inc

Inventors

• Perrott Michael H

Classifications

• H03M7/3004

  Digital delta-sigma modulation · CPC title

• H03L7/0802 Primary

  the loop being adapted for reducing power consumption (H03L7/14 takes precedence) · CPC title

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03M3/358

  of non-linear distortion, e.g. instability (avoiding instability by structural design H03M3/44) · CPC title

• H03M3/368

  of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators · CPC title