Methods for forming protection layers on sidewalls of contact etch stop layers

Patent metadata

Field	Value
Publication number	US-9269809-B2
Application number	US-201414184826-A
Country	US
Kind code	B2
Filing date	Feb 20, 2014
Priority date	Mar 14, 2013
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

When forming semiconductor devices with contact plugs comprising protection layers formed on sidewalls of etch stop layers to reduce the risk of shorts, the protection layers may be formed by performing a sputter process to remove material from a contact region and redeposit the removed material on the sidewalls of the etch stop layers.

First claim

What is claimed:

1. A method, comprising:
providing a device structure comprising a contact region, said contact region comprising a contact region material;
forming a dielectric etch stop layer above said contact region;
forming a dielectric layer above said etch stop layer;
etching an opening into said dielectric layer;
etching said etch stop layer through said opening so as to expose said contact region material of said contact region at the bottom of said opening; and
performing a back-sputter process to remove a portion of said contact region material from said exposed contact region and to re-deposit the removed contact region material within said opening, said re-deposited contact region material covering at least an entirety of exposed sidewalls of said etch stop layer.

2. The method of claim 1 , further comprising performing a wet chemical cleaning process to remove etch by-products from sidewalls of said opening after performing said back-sputter process.

3. The method of claim 1 , further comprising filling said opening with a conductive contact material.

4. The method of claim 2 , wherein said re-deposited contact region material forms a protection layer on said exposed sidewalls of said etch stop layer that protects said etch stop layer during said wet chemical cleaning process.

5. The method of claim 4 , wherein said contact region material and said protection layer comprise a metal silicide.

6. The method of claim 3 , wherein said conductive contact material comprises tungsten.

7. The method of claim 3 , further comprising forming a barrier layer on said protection layer re-deposited contact region material prior to filling said opening with said conductive contact material.

8. The method of claim 1 , wherein said device structure is a field effect transistor and said contact region is provided in at least one of a source region, drain region and a gate electrode of said field effect transistor.

9. The method of claim 1 , wherein said etch stop layer comprises strained silicon nitride.

10. The method of claim 1 , wherein said etch stop layer comprises an intrinsic strain in the range of approximately 1 Gigapascal or more.

11. The method of claim 1 , wherein an etching process that is used to etch said etch stop layer through said opening creates an as-etched damaged region in said etch stop layer.

12. A method, comprising:
forming a silicide region;
forming an etch stop layer above said silicide region;
forming a dielectric layer above said etch stop layer;
etching an opening into said dielectric layer using said etch stop layer as an etch stop;
etching said etch stop layer through said opening so as to expose said silicide region; and
performing a redistribution process to remove silicide material from said exposed silicide region and to re-deposit said removed silicide material within said opening so as to form a silicide layer that covers at least an entirety of exposed sidewalls of said etch stop layer.

13. The method of claim 12 , further comprising performing a wet chemical cleaning process to remove etch by-products from said sidewalls of said opening after performing said redistribution process.

14. The method of claim 13 , wherein an etching process that is used to etch said etch stop layer through said opening creates an as-etched damaged region in said etch stop layer, said silicide layer protecting said as-etched damaged region from exposure to said wet chemical cleaning process.

15. The method of claim 12 , wherein said redistribution process is a sputter back-sputter process.

16. The method of claim 12 , further comprising filling said opening with a conductive contact material.

17. The method of claim 12 , wherein said redistribution process is performed prior to exposing sidewalls of said opening to any wet chemical cleaning processes.

18. A method, comprising:
forming a contact region comprising a conductive material in one of a source region and a drain region of a semiconductor device;
after forming said contact region, forming a dielectric material layer system above said contact region, said dielectric material layer system comprising a first dielectric layer formed above said contact region and a second dielectric layer formed above said first dielectric layer;
performing one or more etching processes to form a contact opening through said dielectric material layer system, said contact opening exposing a portion of said contact region;
performing a material redistribution process to remove a portion of said conductive material from said contact region and to re-deposit said removed portion of said conductive material within said opening, said re-deposited conductive material substantially completely covering at least an entirety of sidewall surfaces of said first dielectric layer; and
performing a wet chemical cleaning process on exposed inside surfaces of said contact opening, said re-deposited conductive material protecting said at least said entirety of said sidewall surfaces of said first dielectric layer from exposure to said wet chemical cleaning process.

19. The method of claim 18 , wherein at least one of said one or more etching processes creates an as-etched damaged material region in said first dielectric layer exposed by said contact opening, said re-deposited conductive material completely covering said as-etched damaged material region.

20. The method of claim 18 , wherein said re-deposited conductive material comprises a protection layer that is formed so as to substantially cover a lower sidewall surface portion of said second dielectric layer and to substantially expose an upper sidewall surface portion of said second dielectric layer.

21. The method of claim 18 , wherein said conductive material comprising said contact region is formed as a metal silicide material having a thickness in the range of approximately 4-30 nm.

22. The method of claim 18 , wherein removing said portion of said conductive material from said contact region comprises forming a recess in said contact region, said recess having a depth in the range of approximately 2-20 nm.

23. The method of claim 18 , wherein re-depositing said conductive material within said opening comprises forming a layer of re-deposited conductive material having a layer thickness of at least approximately 1 nm.

Assignees

• Globalfoundries Inc

Inventors

• Frohberg Kai
• Lepper Marco
• Reiche Katrin

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W20/4435

  Noble-metal alloys · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title