Semiconductor device with a connection pad in a substrate and method for production thereof

Patent metadata

Field	Value
Publication number	US-9269680-B2
Application number	US-201414270104-A
Country	US
Kind code	B2
Filing date	May 5, 2014
Priority date	Aug 24, 2009
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first semiconductor substrate;
a first pad formed on the first semiconductor substrate;
a second semiconductor substrate; and
a second pad formed on the second semiconductor substrate, wherein a size of the second pad is larger than a size of the first pad, wherein the first pad is in contact with a layer formed of a material at least partially covering a surface of the second pad, and wherein a surface of the first pad in contact with the layer formed of the material at least partially covering the surface of the second pad is positioned to face the second pad.

2. The semiconductor device of claim 1 , wherein the first pad includes copper.

3. The semiconductor device of claim 1 , wherein the second pad includes copper.

4. The semiconductor device of claim 1 , wherein the first pad includes copper and the second pad includes copper.

5. The semiconductor device of claim 1 , wherein a portion of the layer formed of a material at least partially covering the surface of the second pad is in contact with the first semiconductor substrate.

6. The semiconductor device of claim 1 , wherein the first pad is formed at least partially within a first interlayer dielectric film.

7. The semiconductor device of claim 6 , wherein the second pad is formed at least partially within a second interlayer dielectric film.

8. The semiconductor device of claim 7 , wherein the first interlayer dielectric film and the second interlayer dielectric film are bonded together.

9. The semiconductor device of claim 1 , wherein at least one of the first semiconductor substrate and the second semiconductor substrate contains a logic device.

10. The semiconductor device of claim 9 , wherein the other of the first semiconductor substrate and the second semiconductor substrate contains memory.

11. The semiconductor device of claim 9 , wherein the logic device includes at least one of a Micro Processing Device (MPU) and a peripheral circuit.

12. The semiconductor device of claim 1 , wherein at least one of the first semiconductor substrate and the second semiconductor substrate contains memory.

13. The semiconductor device of claim 12 , wherein the memory includes at least one of DRAM, SRAM, and flash memory.

14. A semiconductor device comprising:
a first semiconductor substrate;
a first pad formed on the first semiconductor substrate;
a second semiconductor substrate;
a second pad formed on the second semiconductor substrate; and
a layer formed of a material disposed between a surface of the first pad and a surface of the second pad, wherein a size of the surface of the second pad is larger than a size of the surface of the first pad.

15. The semiconductor device of claim 14 , wherein the first pad is formed of copper and the second pad is formed of copper.

16. The semiconductor device of claim 14 , wherein a surface of the first pad is in contact with the layer formed of the material, the surface of the second pad is in contact with the layer formed of the material, and the surface of the first pad is positioned to face the surface of the second pad.

17. The semiconductor device of claim 14 , wherein the second pad includes a base portion and a covering layer portion, the base portion includes a material that is different than the covering portion, the covering portion is flush with a boundary between a first dielectric film and a second dielectric film, and the covering layer portion is the layer formed of a material disposed between a surface of the first pad and a surface of the second pad.

18. A semiconductor device comprising:
a first semiconductor substrate;
a first interlayer dielectric film;
a first wiring layer between the first semiconductor substrate and the first interlayer dielectric film;
a first pad formed at least partially within the first interlayer dielectric film;
a second semiconductor substrate;
a second interlayer dielectric film;
a second wiring layer between the second semiconductor substrate and the second interlayer dielectric film;
a second pad formed at least partially within the second interlayer dielectric film; and
a layer formed of a material disposed between a surface of the first pad and a surface of the second pad.

19. The semiconductor device of claim 18 , wherein a size of the surface of the second pad is larger than a size of the surface of the first pad.

Assignees

• Sony Corp

Inventors

• Okuyama Atsushi

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W90/00

  Package configurations · CPC title