Methods for testing integrated circuits of wafer and testing structures for integrated circuits

Patent metadata

Field	Value
Publication number	US-9269642-B2
Application number	US-201313915947-A
Country	US
Kind code	B2
Filing date	Jun 12, 2013
Priority date	Jun 12, 2013
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

Aspects of the present invention relate to methods of testing an integrated circuit of a wafer and testing structures for integrated circuits. The methods include depositing a sacrificial material over a first conductor material of the integrated circuit, and contacting a test probe to the deposited sacrificial material. The methods can also include testing the integrated circuit using the test probe contacting the sacrificial material. Finally, the methods can include removing the sacrificial material over the first conductor material of the integrated circuit subsequent to the testing of the integrated circuit.

First claim

What is claimed is:

1. A method for testing an integrated circuit in a wafer, the method comprising:
depositing an insulating layer over the integrated circuit including a first conductor material of the integrated circuit;
removing a portion of the insulating layer positioned over the integrated circuit to expose a portion of the first conductor material of the integrated circuit;
depositing a second conductor material over the insulating layer and the exposed portion of the first conductor material;
depositing a sacrificial material over the first conductor material of the integrated circuit,
wherein the depositing of the insulating layer over the integrated circuit including the first conductor material of the integrated circuit is performed prior to the depositing of the sacrificial material;
depositing the sacrificial material over the second conductor material;
removing a portion of the second conductor material after the depositing of the second conductor material;
contacting a test probe to the sacrificial material;
testing the integrated circuit using the test probe contacting the sacrificial material; and
removing the sacrificial material over the first conductor material of the integrated circuit subsequent to the testing of the integrated circuit.

2. The method of claim 1 , wherein the depositing of the sacrificial material includes depositing the sacrificial material over at least a portion of the first conductor material of the integrated circuit.

3. The method of claim 1 , wherein the sacrificial material includes an electrically conductive material.

4. The method of claim 1 , wherein the testing of the integrated circuit includes determining electrical characteristics of the integrated circuit.

5. The method of claim 1 , wherein the contacting of the test probe to the sacrificial material includes positioning the test probe directly above the first conductor material of the integrated circuit.

6. The method of claim 1 , wherein the contacting of the test probe to the sacrificial material includes inserting the test probe a predetermined distance into the sacrificial material based upon a thickness of the sacrificial material.

7. A method for testing an integrated circuit in a wafer, the method comprising:
depositing an insulating layer over the integrated circuit including a first conductor material of the integrated circuit;
removing a portion of the insulating layer positioned over the integrated circuit to expose a portion of the first conductor material of the integrated circuit;
depositing a second conductor material over the insulating layer and the exposed portion of the first conductor material;
removing a portion of the second conductor material deposited over the insulating layer;
depositing a sacrificial material over the second conductor material deposited over the exposed portion of the first conductor material of the integrated circuit, and depositing the sacrificial material over a portion of the insulating layer,
wherein the removing of the portion of the insulating layer positioned over the integrated circuit to expose the portion of the first conductor material of the integrated circuit is performed prior to the depositing of the sacrificial material over the second conductor material;
contacting a test probe to the sacrificial material;
testing the integrated circuit using the test probe contacting the sacrificial material; and
removing the sacrificial material over the second conductor material, subsequent to the testing of the integrated circuit.

8. The method of claim 7 , wherein the sacrificial material includes an electrically conductive material.

9. The method of claim 7 , wherein the testing of the integrated circuit includes determining electrical characteristics of the integrated circuit.

10. The method of claim 7 , wherein the contacting of the test probe to the sacrificial material includes positioning the test probe directly above the first conductor material of the integrated circuit.

11. The method of claim 7 , wherein the contacting of the test probe to the sacrificial material includes inserting the test probe a predetermined distance into the sacrificial material based upon a thickness of the sacrificial material.

12. The method of claim 7 , further comprising:
prior to the inserting of the test probe partially through the sacrificial material, removing a portion of the second conductor material.

13. The method of claim 7 , wherein the depositing of the sacrificial material includes depositing the sacrificial material over at least a portion of the first conductor material of the integrated circuit.

Assignees

• Globalfoundries Inc

Inventors

• Coster Michael T
• Dirocco Mark A
• Gambino Jeffrey P
• Peterson Kirk D

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10P74/207 Primary

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H01L23/481

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic