Resistive memory apparatus and write-in method thereof

Patent metadata

Field	Value
Publication number	US-9269434-B2
Application number	US-201414203585-A
Country	US
Kind code	B2
Filing date	Mar 11, 2014
Priority date	Nov 26, 2013
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A resistive memory apparatus and a write-in method thereof are provided. The memory controller provides unselected bit-lines and unselected word-lines both not coupled to a selected resistive memory cell respectively with a first bit-line voltage and a first word-line voltage in one of a setting duration and a resetting duration, wherein the first bit-line voltage is equal to a product of a writing-in voltage V W and (n−1)/n and the first word-line voltage is equal to V W ×1/n. The memory controller provides the unselected bit-lines not coupled to the selected resistive memory cell with a second bit-line voltage and the unselected word-lines not coupled to the selected resistive memory cell with a second word-line voltage in the other one of the setting duration and the resetting duration, wherein the second bit-line voltage is equal to V W ×1/n and the second word-line voltage is equal to V W ×(n−1)/n.

First claim

What is claimed is:

1. A resistive memory apparatus, comprising:
a memory cell array, comprising a plurality of memory unit, wherein each of the memory units comprises a plurality of stacked resistive memory cells, the resistive memory cells are respectively coupled to a plurality of word-lines and the memory units are respectively coupled to a plurality of bit-lines; and
a memory controller, coupled to the memory cell array, wherein, the memory controller provides a plurality of unselected bit-lines not coupled to a selected resistive memory cell with a first bit-line voltage and a plurality of unselected word-lines not coupled to the selected resistive memory cell with a first word-line voltage in one of a setting duration and a resetting duration, wherein the first bit-line voltage is equal to a product of a first writing-in voltage V W1 and (n−1)/n, and the first word-line voltage is equal to V W1 ×1/n, wherein n is a real number greater than 3,
the memory controller provides the unselected bit-lines not coupled to the selected resistive memory cell with a second bit-line voltage and the unselected word-lines not coupled to the selected resistive memory cell with a second word-line voltage in the other one of the setting duration and the resetting duration, wherein the second bit-line voltage is equal to a product of a second writing-in voltage V W2 and 1/n, and the second word-line voltage is equal to V W2 ×(n−1)/n.

2. The resistive memory apparatus as claimed in claim 1 , wherein the memory controller provides a selected word-line coupled to the selected resistive memory cell with a reference grounding voltage and a selected bit-line coupled to the selected resistive memory cell with the first and second writing-in voltages in the setting duration and the resetting duration.

3. The resistive memory apparatus as claimed in claim 1 , wherein characteristic relation between current and voltage for a resetting state of each the resistive memory cell and characteristic relation between current and voltage for a setting state of each the resistive memory cell are not symmetric with each other.

4. The resistive memory apparatus as claimed in claim 1 , wherein the memory units are arranged in array.

5. A write-in method of resistive memory, comprising:
providing a plurality of unselected bit-lines not coupled to a selected resistive memory cell with a first bit-line voltage and a plurality of unselected word-lines not coupled to the selected resistive memory cell with a first word-line voltage in one of a setting duration and a resetting duration, wherein the first bit-line voltage is equal to a product of a first writing-in voltage V W1 and (n−1)/n, and the first word-line voltage is equal to V W1 ×1/n, wherein n is a real number greater than 3; and
providing the unselected bit-lines not coupled to the selected resistive memory cell with a second bit-line voltage and the unselected word-lines not coupled to the selected resistive memory cell with a second word-line voltage in the other one of the setting duration and the resetting duration, wherein the second bit-line voltage is equal to a product of a second writing-in voltage V W2 ×1/n and the second word-line voltage is equal to V W2 ×(n−1)/n.

6. The write-in method of resistive memory as claimed in claim 5 , further comprising:
providing a selected word-line coupled to the selected resistive memory cell with a reference grounding voltage and a selected bit-line coupled to the selected resistive memory cell with the first and second writing-in voltages in the setting duration and the resetting duration.

7. The write-in method of resistive memory as claimed in claim 5 , wherein the resistive memory comprises a plurality of resistive memory cells, and characteristic relation between current and voltage for a resetting state of each the resistive memory cell and characteristic relation between current and voltage for a setting state of each the resistive memory cell are not symmetric with each other.

Assignees

• Winbond Electronics Corp

Inventors

• Hou Tuo-Hung
• Hsu Chung-Wei
• Chen Mei-Chin

Classifications

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title