Victim cache that supports draining write-miss entries
US-2024264952-A1 · Aug 8, 2024 · US
US9268703B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9268703-B2 |
| Application number | US-42444409-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 15, 2009 |
| Priority date | Apr 15, 2009 |
| Publication date | Feb 23, 2016 |
| Grant date | Feb 23, 2016 |
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Official abstract text for this publication.
A technique for performing cache injection in a processor system includes monitoring, by a cache, addresses on a bus. Input/output data associated with an address of a data block stored in the cache is then requested from a remote node, via a network controller. Ownership of the input/output data is acquired by the cache when an address on the bus that is associated with the input/output data corresponds to the address of the data block stored in the cache.
Opening claim text (preview).
What is claimed is: 1. A method of performing cache injection in a processor system, comprising: detecting, by a cache, a specific instruction sequence that includes multiple instructions, wherein one of the multiple instructions is a load instruction to a first address and another one of the multiple instructions is a compare instruction; monitoring, by the cache, addresses on a bus in response to detecting the specific instruction sequence multiple times; requesting, from a…
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