Apparatus and method for vectorization with speculation support

Patent metadata

Field	Value
Publication number	US-9268626-B2
Application number	US-201113997664-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 23, 2011
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.

First claim

We claim:

1. A processor for providing speculation support enabling vectorization, the processor to execute one or more instructions to perform the operations of:
reading each active element in succession from an input vector register, each active element specifying an address for a gather or load operation;
detecting one or more fault conditions associated with one or more of the active elements;
for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing data loaded from an address associated with the active element in an output vector register;
for each active element associated with the detected fault condition and following the detected fault condition;
setting a bit in an output mask register to indicate the detected fault condition, and
storing data loaded from the active element in the output vector register if the active element is not the first active element; and

performing the gather or load operation on the active elements based on the loaded data.

2. The processor as in claim 1 to perform the additional operations of:
storing data loaded from an address associated with the first active element after servicing any detected fault condition in the output vector register.

3. The processor as in claim 1 to perform the additional operations of:
reading each bit in succession from an input mask register, each bit having a true value to indicate each active element read from the input vector register and a false value to indicate each inactive element read from the input vector register.

4. The processor as in claim 3 wherein the input mask register comprises the same physical register as the output mask register.

5. The processor as in claim 1 to perform the additional operations of:
adding a base address value to each address read from the input vector register to arrive at a memory address for the gather or load operation; and
storing data loaded from each memory address in the output vector register for each active element prior to the detected fault condition.

6. A method comprising:
reading each active element in succession from an input vector register, each active element specifying an address for a gather or load operation by a processor;
detecting one or more fault conditions associated with one or more of the active elements;
for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing data loaded from the address associated with the active element in an output vector register;
for each active element associated with the detected fault condition and following the detected fault condition;
setting a bit in an output mask register to indicate the detected fault condition, and
storing data loaded from the active element in the output vector register if the active element is not the first active element; and

performing the gather or load operation by the processor on the active elements based on the loaded data.

7. The method claim 6 further comprising:
storing data loaded from an address associated with the first active element after servicing any detected fault condition in the output vector register.

8. The method as in claim 6 further comprising:
reading each bit in succession from an input mask register, each bit having a true value to indicate each active element read from the input vector register and a false value to indicate each inactive element read from the input vector register.

9. The method as in claim 8 wherein the input mask register comprises the same physical register as the output mask register.

10. The method as in claim 6 further comprising:
adding a base address value to each address read from the input vector register to arrive at a memory address for the gather or load operation; and
storing data loaded from each memory address in the output vector register for each active element prior to the detected fault condition.

11. A computer system comprising:
a memory for storing program instructions and data;
a processor to execute one or more of the program instructions to perform the operations of:
reading each active element in succession from an input vector register, each active element specifying an address for a gather or load operation;
detecting one or more fault conditions associated with one or more of the active elements;
for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the address associated with the active element in an output vector register;
for each active element associated with the detected fault condition and following the detected fault condition;
setting a bit in an output mask register to indicate the detected fault condition, and
storing data loaded from the active element associated in the output vector register if the active element is not the first active element; and

performing the gather or load operation on the active elements based on the loaded data.

12. The system as in claim 11 wherein the processor is to perform the additional operations of:
storing data loaded from an address associated with the first active element after servicing any detected fault condition in the output vector register.

13. The system as in claim 11 wherein the processor is to perform the additional operations of:
reading each bit in succession from an input mask register, each bit having a true value to indicate each active element read from the input vector register and a false value to indicate each inactive element read from the input vector register.

14. The system as in claim 13 wherein the input mask register comprises the same physical register as the output mask register.

15. The system as in claim 11 wherein the processor is to perform the additional operations of:
adding a base address value to each address read from the input vector register to arrive at a memory address for the gather or load operation; and
storing data loaded from each memory address in the output vector register for each active element prior to the detected fault condition.

16. The computer system as in claim 15 further comprising:
a user input interface to receive control signals from a user input device, the processor executing the program instructions in response to the control signals.

17. The computer system as in claim 11 further comprising:
a display adapter to render graphics images in response to execution of the program instructions by the processor.

Assignees

• Bharadwaj Jayashankar
• Lee Victor W
• Daehyun Kim
• Vasudevan Nalini
• Ngai Tin-Fook
• Hartono Albert
• Baghsorkhi Sara S
• Intel Corp

Inventors

• Bharadwaj Jayashankar
• Lee Victor W
• Daehyun Kim
• Vasudevan Nalini
• Ngai Tin-Fook
• Hartono Albert
• Baghsorkhi Sara S

Classifications

• G06F9/30018 Primary

  Bit or string instructions · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F11/0751 Primary

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30038

  using a mask · CPC title