Modify and execute next sequential instruction facility and instructions therefor

Patent metadata

Field	Value
Publication number	US-9268572-B2
Application number	US-201213710494-A
Country	US
Kind code	B2
Filing date	Dec 11, 2012
Priority date	Dec 11, 2012
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

An modify next sequential instruction (MNSI) instruction, when executed, modifies a field of the fetched copy of the next sequential instruction (NSI) to enable a program to dynamically provide parameters to the NSI being executed. Thus the MNSI instruction is a non-disruptive prefix instruction to the NSI. The NSI may be modified to effectively extend the length of the NSI field, thus providing more registers or more range (in the case of a length field) than otherwise available to the NSI instruction according to the instruction set architecture (ISA).

First claim

What is claimed is:

1. A computer program product, the computer program product comprising a non-transitory computer readable storage medium having program code embodied therewith, the program code readable by the computer to perform a method comprising:
fetching, by a processor, at an address specified by a program counter a prefix machine instruction and a first next sequential instruction (NSI), the prefix machine instruction and the first NSI defined for a computer architecture, the first NSI directly following the prefix machine instruction in program order; and
executing the fetched prefix machine instruction and first NSI, the executing comprising a)-c):
a) modifying a field of the fetched first NSI based on a value specified by the prefix machine instruction to produce a modified first NSI;
b) executing the modified first NSI; and
c) incrementing the program counter to point to a second NSI, the second NSI directly following the first NSI in program order; and

executing the second NSI.

2. The computer program product according to claim 1 , wherein the field of the first NSI consists of any one of an immediate field, an index field or a length field.

3. The computer program product according to claim 1 , wherein the prefix instruction further comprises a prefix register field, the modifying further comprising:
obtaining the value from a register specified by the prefix register field; and
replacing the field of the fetched first NSI with a replacement value based on the value specified by the prefix machine instruction.

4. The computer program product according to claim 3 , wherein based on the prefix register field being any one of one or more prefix register field values, the modifying further comprising:
obtaining the value from a low order portion of the register specified by the prefix register field; and
performing any one of a logical OR, AND or EXCLUSIVE OR of the value with the field of the fetched first NSI to form the replacement value.

5. The computer program product according to claim 3 , wherein the method further comprises:
based on an opcode field of the first NSI comprising bits of the field of the fetched first NSI, aborting executing the fetched prefix machine instruction and first NSI and signaling an error condition.

6. The computer program product according to claim 3 , wherein the method further comprises:
based on information provided by the prefix machine instruction, determining a location in the fetched first NSI of the field of the fetched first NSI.

7. The computer program product according to claim 6 , wherein the method further comprises:
extracting the information from a register specified by the prefix machine instruction, the information defining the location of the field of the first NSI.

8. The computer program product according to claim 1 , wherein the field of the modified NSI is larger than the field of the NSI, wherein the field of the modified NSI comprises a value greater than any value supported by the field of the NSI.

9. A computer system comprising:
a memory; and
a processor coupled to said memory, the processor comprising an instruction fetch unit and an execution unit, the processor configured to perform a method comprising:
fetching, by the processor, at an address specified by a program counter a prefix machine instruction and a first next sequential instruction (NSI), the prefix machine instruction and the first NSI defined for a computer architecture, the first NSI directly following the prefix machine instruction in program order; and
executing the fetched prefix machine instruction and first NSI, the executing comprising a)-c):
a) modifying a field of the fetched first NSI based on a value specified by the prefix machine instruction to produce a modified first NSI;
b) executing the modified first NSI; and
c) incrementing the program counter to point to a second NSI, the second NSI directly following the first NSI in program order; and

executing the second NSI.

10. The computer system according to claim 9 , wherein the field of the first NSI consists of any one of an immediate field, an index field or a length field.

11. The computer system according to claim 9 , wherein the prefix instruction further comprises a prefix register field, the modifying further comprising:
obtaining the value from a register specified by the prefix register field; and
replacing the field of the fetched first NSI with a replacement value based on the value specified by the prefix machine instruction.

12. The computer system according to claim 11 , wherein based on the prefix register field being any one of one or more prefix register field values, the modifying further comprising:
obtaining the value from a low order portion of the register specified by the prefix register field; and
performing any one of a logical OR, AND or EXCLUSIVE OR of the value with the field of the fetched first NSI to form the replacement value.

13. The computer system according to claim 11 , wherein the method further comprises:
based on an opcode field of the first NSI comprising bits of the field of the fetched first NSI, aborting executing the fetched prefix machine instruction and first NSI and signaling an error condition.

14. The computer system according to claim 11 , wherein the method further comprises:
based on information provided by the prefix machine instruction, determining a location in the fetched first NSI of the field of the fetched first NSI.

15. The computer system according to claim 14 , wherein the method further comprises:
extracting the information from a register specified by the prefix machine instruction, the information defining the location of the field of the first NSI.

16. The computer system according to claim 9 , wherein the field of the modified NSI is larger than the field of the NSI, wherein the field of the modified NSI comprises a value greater than any value supported by the field of the NSI.

Assignees

• IBM

Inventors

• Gschwind Michael K
• Schwarz Eric M

Classifications

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title

• G06F9/30054 Primary

  Unconditional branch instructions · CPC title

• G06F9/30058

  Conditional branch instructions · CPC title

• G06F9/342

  Extension of operand address space · CPC title