Latch Performance Detection Method, Device and Electronic Device
US-2024170092-A1 · May 23, 2024 · US
US9267980B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9267980-B2 |
| Application number | US-201113210264-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 15, 2011 |
| Priority date | Aug 15, 2011 |
| Publication date | Feb 23, 2016 |
| Grant date | Feb 23, 2016 |
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Official abstract text for this publication.
Apparatus and methods for evaluating leakage currents of capacitances are described. Capacitances having excessive leakage currents may be disabled from use. An example apparatus includes a leakage detection circuit configured to be coupled to a capacitance block. The leakage detection circuit is configured to determine whether a leakage current of a capacitance of the capacitance block exceeds a current limit and is further configured to provide an output indicative of a status of the capacitance. A detection controller is coupled to the leakage detection circuit and a register, and the detection controller is configured to store data in the register indicative of the status of the capacitance based at least in part on the signal from the leakage detection circuit.
Opening claim text (preview).
What is claimed is: 1. An apparatus, comprising: a leakage detection circuit configured to be coupled to a capacitance block, the leakage detection circuit configured to determine whether a leakage current of a capacitance of the capacitance block exceeds a reference current and further configured to provide an output indicative of a status of the capacitance, the leakage detection circuit including an output circuit having an input node and an output node, the output circuit configured to receive both the leakage and reference currents at the same input node, and based at least in part on the leakage and reference currents provide the output from the output node having a logic level indicative of whether the leakage current exceeds the reference current; a register; and a controller coupled to the leakage detection circuit and the register, the controller configured to store data in the register indicative of the status of the capacitance based at least in part on the output from the leakage detection circuit. 2. The apparatus of claim 1 wherein the leakage detection circuit comprises: a measurement circuit configured to be coupled to the capacitance and further configured to apply a test voltage to the capacitance and provide the leakage current; and a reference circuit configured to provide a reference current. 3. The apparatus of claim 2 wherein the reference circuit comprises a current mirror configured to receive the reference current and mirror the same to the output circuit. 4. The apparatus of claim 2 wherein the measurement circuit comprises: measurement circuit configured to provide the test voltage to the capacitance and to provide a resultant leakage current; and a current mirror coupled to the measurement circuit and configured to mirror the resultant leakage current as the leakage current. 5. The apparatus of claim 4 wherein the measurement circuit comprises a negative feedback configured amplifier configured to be coupled to a test voltage supply and further configured to provide an output voltage responsive to a bias voltage provided to a negative input and a voltage provided to a positive input; a first transistor coupled to the negative feedback configured amplifier and configured to be coupled to the test voltage supply, the first transistor configured to couple the capacitance and the positive voltage input to the bias voltage supply responsive to the output voltage of the negative feedback configured amplifier; and a second transistor coupled to the negative feedback configured amplifier and configured to be coupled to the test voltage supply, the second transistor having substantially similar transistor characteristics as the first transistor and configured to provide the resultant leakage current to the current mirror responsive to the output voltage of the negative feedback configured amplifier. 6. The apparatus of claim 2 wherein the output circuit comprises an inverter.
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