Transistors, memory cells and semiconductor constructions

Patent metadata

Field	Value
Publication number	US-9263672-B2
Application number	US-201414331026-A
Country	US
Kind code	B2
Filing date	Jul 14, 2014
Priority date	Nov 20, 2012
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

First claim

We claim:

1. A semiconductor construction, comprising:
a semiconductor base;
a gate extending into the base; a region of the base on one side of the gate being a conductively-doped source region, and a region of the base on an opposing side of the gate relative to said one side being a conductively-doped drain region; the drain region being more heavily doped than the source region;
a gate dielectric comprising a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments;
wherein the gate dielectric, along a cross-section, is configured as an upwardly-opening container having the gate therein; wherein the first segment of the gate dielectric comprises a first substantially vertical leg of the container, wherein the second segment of the gate dielectric comprises a second substantially vertical leg of the container, and wherein the third segment of the gate dielectric comprises a bottom of the container;
the gate dielectric comprising non-ferroelectric material directly against ferroelectric material, with the non-ferroelectric material being a boundary of the container directly against the semiconductor base; and
wherein the non-ferroelectric material is thicker along the bottom of the container than along the first and second substantially vertical legs of the container.

2. The semiconductor construction of claim 1 wherein the non-ferroelectric material comprises one or both of silicon dioxide and silicon nitride.

3. The semiconductor construction of claim 1 further comprising a capacitor electrically coupled to the drain region.

4. The semiconductor construction of claim 1 wherein the source region comprises a dopant gradient in which dopant concentration is lighter in a location relatively deep within the source region as compared to a location relatively shallow within the source region.

5. The semiconductor construction of claim 1 wherein the ferroelectric material comprises one or more of Hf, Zr, Si, O, Y, Ba, Mg and Ti.

6. The semiconductor construction of claim 1 wherein the non-ferroelectric material comprises a thickness within the first and second segments within a range of from about 10 angstroms to about 20 angstroms, and comprises a thickness within the third segment within a range of from about 25 angstroms to about 50 angstroms.

7. A semiconductor construction, comprising:
a semiconductor base;
a gate extending into the base; a region of the base on one side of the gate being a doped source region, and a region of the base on an opposing side of the gate relative to said one side being a doped drain region; the drain region being more heavily doped than the source region;
a gate dielectric comprising a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments;
wherein the gate dielectric, along a cross-section, is configured as an upwardly-opening container having the gate therein, and wherein the third segment of the gate dielectric comprises a bottom of the container;
the gate dielectric comprising non-ferroelectric material directly against ferroelectric material, with the non-ferroelectric material being a boundary of the container directly against the semiconductor base; and
wherein the non-ferroelectric material is thicker along the bottom of the container than along the first and second segments of the gate dielectric.

Assignees

• Micron Technology Inc

Inventors

• Ramaswamy Durai Vishak Nirmal
• Prall Kirk D
• Kinney Wayne

Classifications

• G11C14/0027

  and the nonvolatile element is a ferroelectric element · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D30/0415

  of FETs having ferroelectric gate insulators · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title