Metal oxide semiconductor transistor and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9219140-B2
Application number	US-201514592872-A
Country	US
Kind code	B2
Filing date	Jan 8, 2015
Priority date	Nov 9, 2011
Publication date	Dec 22, 2015
Grant date	Dec 22, 2015

Abstract

The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor.

First claim

What is claimed is:

1. A MOS transistor, comprising:
a substrate;
a gate dielectric layer disposed on the substrate;
a gate disposed on the gate dielectric layer;
a source/drain region disposed in the substrate at two sides of the gate; and
a silicide layer disposed on a part of the source/drain region, wherein the silicide layer comprises a curved bottom surface and a curved top surface, wherein both the curved top surface and the curved bottom surface of the silicide layer bends toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure.

2. The MOS transistor as in claim 1 , further comprising a contact plug directly contacting the silicide layer, wherein an area of a top surface of the silicide layer is substantially greater than that of a bottom surface of the contact plug.

3. The MOS transistor as in claim 1 , wherein the top surface of the silicide layer is substantially lower than a top surface of the gate.

4. The MOS transistor as in claim 1 , wherein the silicide layer comprises NiSi, CoSi or TiSi.

5. The MOS transistor as in claim 1 , further comprising a sacrificial layer disposed on the substrate, wherein the sacrificial layer only levels with the gate.

6. The MOS transistor as in claim 1 , further comprising a sacrificial layer disposed on the substrate, wherein the sacrificial layer only levels with the source/drain region.

7. The MOS transistor as in claim 1 , wherein the source/drain region comprises an epitaxial layer.

Assignees

• United Microelectronics Corp

Inventors

• Chiang Wen-Tai
• Lin Chun-Hsien

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10D64/0112 Primary

  using conductive layers comprising silicides · CPC title

• H10D62/021

  Forming source or drain recesses by etching e.g. recessing by etching and then refilling · CPC title