Semiconductor device including a normally-off transistor and transistor cells of a normally-on GaN HEMT

Patent metadata

Field	Value
Publication number	US-9263443-B2
Application number	US-201313963080-A
Country	US
Kind code	B2
Filing date	Aug 9, 2013
Priority date	Mar 19, 2010
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

A semiconductor device includes a first semiconductor die including a normally-off transistor and a second semiconductor die including a plurality of transistor cells of a normally-on GaN HEMT. One of a source terminal and a drain terminal of the normally-off transistor is electrically coupled to a gate terminal of the normally-on GaN HEMT, and the other one of the source terminal and the drain terminal of the normally-off transistor is electrically coupled to one of a source terminal and a drain terminal of the normally-on GaN HEMT. The second semiconductor die further includes a gate resistor electrically coupled between the gate terminal of the normally-off transistor and respective gates of the plurality of transistor cells, and a voltage clamping element electrically coupled between the gate terminal and one of the source terminal and the drain terminal of the normally-on GaN HEMT.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first semiconductor die including a normally-off transistor; and
a second semiconductor die including a plurality of transistor cells of a normally-on GaN HEMT, one of a source terminal and a drain terminal of the normally-off transistor being electrically coupled to a gate terminal of the normally-on GaN HEMT, the other one of the source terminal and the drain terminal of the normally-off transistor being electrically coupled to one of a source terminal and a drain terminal of the normally-on GaN HEMT,
wherein the second semiconductor die further includes:
a gate resistor electrically coupled between the gate terminal of the normally-on transistor and respective gates of the plurality of transistor cells; and
a voltage clamping element electrically coupled between the gate terminal and the one of the source terminal and the drain terminal of the normally-on GaN HEMT.

2. The semiconductor device of claim 1 , wherein the first semiconductor die includes a semiconductor substrate made of Si and the normally-off transistor is a normally-off metal insulator field effect transistor (MISFET).

3. The semiconductor device of claim 1 , wherein the voltage clamping element includes a pn junction diode.

4. The semiconductor device of claim 1 , wherein a clamping voltage of the voltage clamping element is smaller than an electrical breakdown voltage between the source and drain of the normally-off transistor.

5. The semiconductor device of claim 1 , wherein the gate resistor is within a range of 0.5Ω to 500Ω.

6. The semiconductor device of claim 1 , wherein a ratio of electrical breakdown voltages of the normally-off transistor and the normally-on GaN HEMT is within a range of 1:5 to 1:100.

7. The semiconductor device of claim 1 , wherein an area of the gate resistor at least partially overlaps with a gate pad area electrically coupled to the gate terminal of the normally-on GaN HEMT.

8. The semiconductor device of claim 3 , wherein both the pn junction diode and the transistor cells of the normally-on GaN HEMT have striped-shaped geometries, the pn junction diode extending in parallel to the transistor cells.

9. The semiconductor device of claim 1 , wherein the first semiconductor die and the second semiconductor die are arranged chip-on-chip in a single package in a sequence of a leadframe, the second semiconductor die and the first semiconductor die.

10. The semiconductor device of claim 9 , wherein the single package includes a gate pin, a source pin and a drain pin, the gate pin being electrically coupled to the gate terminal of the normally-on transistor, the source pin being electrically coupled to the one of the source terminal and the drain terminal of the normally-off transistor, the drain pin being electrically coupled to the other one of the source terminal and the drain terminal of the normally-on GaN HEMT.

Assignees

• Infineon Technologies Austria

Inventors

• Treu Michael
• Siemieniec Ralf

Classifications

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/343

  Gate regions of field-effect devices having PN junction gates · CPC title

• H10D62/149

  Source or drain regions of field-effect devices · CPC title

• H10D1/43

  Resistors having PN junctions · CPC title