Apparatus related to a diode device including a JFET portion

Patent metadata

Field	Value
Publication number	US-9263438-B2
Application number	US-201213427541-A
Country	US
Kind code	B2
Filing date	Mar 22, 2012
Priority date	Mar 22, 2012
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

In one general aspect, an apparatus can include an anode terminal, and a cathode terminal. The apparatus can include a junction field-effect transistor (JFET) portion having a channel disposed within a semiconductor substrate and defining a first portion of an electrical path between the anode terminal and the cathode terminal. The apparatus can also include a diode portion formed within the semiconductor substrate and defining a second portion of the electrical path between the anode terminal and the cathode terminal. The diode portion can be serially coupled to the channel of the JFET device.

First claim

What is claimed is:

1. An apparatus, comprising:
an anode terminal;
a cathode terminal;
a semiconductor substrate;
an epitaxial layer disposed on the semiconductor substrate;
an isolation region including a first heavily doped portion and a second heavily doped portion;
a well region disposed between the isolation region and the cathode;
a junction field-effect transistor (JFET) portion having a channel disposed within the semiconductor substrate and defining a first portion of an electrical path between the anode terminal and the cathode terminal, the first portion of the electrical path including the first heavily doped portion; and
a diode portion formed within the semiconductor substrate and defining a second portion of the electrical path between the anode terminal and the cathode terminal, the diode portion being serially coupled to the channel of the JFET portion, the second portion of the electrical path including the second heavily doped portion.

2. The apparatus of claim 1 , wherein current flows from the anode terminal to the cathode terminal through the channel of the JFET portion when the diode portion is forward biased, and current is substantially prevented from flowing from the cathode terminal to the anode terminal through the channel of the JFET portion when the channel of the JFET portion is depleted and the diode portion is reverse biased.

3. The apparatus of claim 1 , further comprising:
an isolation region disposed below the anode terminal and the cathode terminal, the channel being disposed within the isolation region and having a first dopant type different from a second dopant type of the semiconductor substrate.

4. The apparatus of claim 1 , further comprising:
an isolation region having a heavily doped portion disposed below the anode terminal.

5. The apparatus of claim 1 , further comprising:
an isolation region having a first heavily doped portion disposed below the anode terminal and a second heavily doped portion disposed below the cathode terminal, the first heavily doped portion being isolated from the second heavily doped portion by a lightly doped portion of the isolation region.

6. The apparatus of claim 1 , further comprising:
an isolation region, the channel being disposed within a portion of the isolation region having a dopant concentration lower than a dopant concentration of a portion of the isolation region disposed below at least one of the anode terminal or the cathode terminal.

7. The apparatus of claim 1 , further comprising:
a ground terminal of the JFET portion disposed between the anode terminal and the cathode terminal.

8. The apparatus of claim 1 , wherein at least a portion of the diode portion and at least a portion of the channel are formed within a common epitaxial layer.

9. The apparatus of claim 1 , wherein a voltage drop between the anode terminal and the cathode terminal when the diode portion is forward biased is approximately two times a forward bias voltage of the diode portion.

10. The apparatus of claim 1 , wherein the diode portion includes a Schottky diode.

11. An apparatus, comprising:
an anode terminal;
a cathode terminal;
a semiconductor substrate;
an epitaxial layer disposed on the semiconductor substrate;
an isolation region overlapping the epitaxial layer and the semiconductor substrate, the isolation region having a first heavily doped portion disposed below the anode terminal, having a second heavily doped portion disposed below the cathode terminal, and having a lightly doped portion disposed between the first heavily doped portion and the second heavily doped portion;
a junction field-effect transistor (JFET) portion having a channel disposed within the isolation region; and
a diode portion including a PN junction having at least a portion disposed between the anode terminal and the heavily doped portion of the isolation region.

12. The apparatus of claim 11 , wherein the isolation region is disposed within the semiconductor substrate and is doped with a first dopant type,
the apparatus further comprising:
a ground terminal of the JFET portion disposed between the anode terminal and the cathode terminal, the anode terminal being in contact with a first portion of the semiconductor substrate doped with a second dopant type, the cathode being in contact with a second portion of the semiconductor substrate doped with the first dopant type, a third portion of the semiconductor substrate disposed between the ground terminal and the isolation region being doped with the second dopant type.

13. The apparatus of claim 11 , wherein
the channel of the isolation region is disposed between the first heavily doped portion and the second heavily doped portion.

14. The apparatus of claim 11 , wherein the channel defines a first portion of an electrical path between the anode terminal and the cathode terminal, the diode portion defines a second portion of the electrical path between the anode terminal and the cathode terminal, and the diode portion is serially coupled to the channel of the JFET portion.

15. The apparatus of claim 11 , wherein current flows from the anode terminal to the cathode terminal through the channel of the JFET portion when the diode portion is forward biased.

16. The apparatus of claim 11 , wherein the JFET portion is configured to function as a blocking component when the channel of the JFET portion is depleted and the diode portion is reverse biased.

17. The apparatus of claim 11 , wherein the isolation region has a first dopant type different from a second dopant type of a semiconductor substrate including the JFET portion and the diode portion.

18. The apparatus of claim 11 , wherein the heavily doped portion is a first heavily doped portion isolated from a second heavily doped portion by the lightly doped portion of the isolation region,
the first heavily doped portion, the second heavily, and the isolation region are doped with the same type of dopant.

19. An apparatus, comprising:
an isolation region having a first dopant type and having at least a portion defining a channel of a junction field-effect transistor (JFET) portion, the isolation region is disposed in a portion of an epitaxial layer and in at least a portion of a semiconductor substrate;
a PN junction serially coupled to the isolation region and included in a diode portion;
a first buried layer disposed in the isolation region and having the first dopant type, the first buried layer being included in the diode portion;
a second buried layer disposed in the isolation region and having the first dopant type, the second buried layer being included in the JFET portion;
a first well region in the JFET portion having a second dopant type different from the first dopant type;
a second well region in the JFET portion having the first dopant type, and being disposed between the second buried layer and a conductive contact; and
a sink having the first dopant type and being included in the diode portion.

20. The apparatus of claim 19 , wherein the semiconductor substrate is common to the JFET portion and the diode portion.

21. The apparatus of claim 19 , wherein the sink is in contact with the first buried layer.

22. The apparatus of claim 19 , wherein the first buried layer is disposed below an anode terminal and below the sink, the first buried layer has a concentration of the first dopant type greater than a concentration of the first dopant type of the isolation region.

Assignees

• Kim Sunglyong
• Kim Jongjib
• Fairchild Semiconductor

Inventors

• Kim Sunglyong
• Kim Jongjib

Classifications

• H10D84/811 Primary

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D84/87

  of PN-junction gate FETs · CPC title

• H10D64/111

  Field plates · CPC title

• H10D12/212

  having PN junction gates, e.g. field controlled diodes · CPC title

• H10D8/80

  PNPN diodes, e.g. Shockley diodes or break-over diodes · CPC title