Discrete semiconductor device package and manufacturing method

Patent metadata

Field	Value
Publication number	US-9263335-B2
Application number	US-201514607587-A
Country	US
Kind code	B2
Filing date	Jan 28, 2015
Priority date	Jun 1, 2012
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

Disclosed is a discrete semiconductor device package ( 100 ) comprising a semiconductor die ( 110 ) having a first surface and a second surface opposite said first surface carrying a contact ( 112 ); a conductive body ( 120 ) on said contact; an encapsulation material ( 130 ) laterally encapsulating said conductive body; and a capping member ( 140, 610 ) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap ( 150 ) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.

First claim

The invention claimed is:

1. A method of manufacturing a discrete semiconductor package, comprising:
providing a wafer comprising a plurality of discrete semiconductor devices, each of said discrete semiconductor devices having a first surface and a second surface opposite said first surface carrying a contact;
forming respective conductive bodies on each of said contacts;
covering at least the surface of the wafer carrying the conductive bodies with an encapsulating material;
singulating the discrete semiconductor devices;
providing a capping member over at least the conductive body of each of the discrete semiconductor devices;
wherein providing the capping member comprises providing a solder cap on each singulated discrete semiconductor device, device; and
the method further comprising providing a further solder cap over the first surface of each of the discrete semiconductor devices.

2. The method of claim 1 , further comprising thinning the wafer surface including the respective first surfaces of the discrete semiconductor devices prior to said singulation step.

3. The method of claim 1 , wherein said singulation step comprises dicing or plasma-etching the wafer to provide the discrete semiconductor devices.

4. The method of claim 1 , wherein the step of providing said capping member further comprises providing a further semiconductor wafer on said respective conductive bodies.

5. A method of manufacturing a discrete semiconductor package, comprising:
providing a wafer comprising a plurality of discrete semiconductor devices, each of said discrete semiconductor devices having a first surface and a second surface opposite said first surface carrying a contact;
forming respective conductive bodies on each of said contacts;
covering at least the surface of the wafer carrying the conductive bodies with an encapsulating material;
singulating the discrete semiconductor devices; and
providing a capping member over at least the conductive body of each of the discrete semiconductor devices;
partially singulating the discrete semiconductor devices prior to said covering step, thereby exposing the sides of each discrete semiconductor device that connect the first surface to the second surface; and
wherein said covering step further comprises covering said sides with the encapsulating material.

6. The method of claim 5 , further comprising:
placing the wafer on a sawing foil prior to said partial singulation step; and
stretching the sawing foil following said partial singulation step to expose the respective sides of the discrete semiconductor devices.

7. The method of claim 5 , wherein the partial singulation step comprises sawing the wafer with a sawing blade having a first thickness, and wherein said singulation step comprises sawing the encapsulated wafer with a sawing blade having a second thickness that is smaller than the first thickness.

Assignees

• Nxp Bv

Inventors

• Boettcher Tim
• Walczyk Sven
• Groenhuis Roelf Anco Jacob
• Brenner Rolf
• De Bruin Emiel

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title