Via structure for packaging and a method of forming

Patent metadata

Field	Value
Publication number	US-9263302-B2
Application number	US-201414186698-A
Country	US
Kind code	B2
Filing date	Feb 21, 2014
Priority date	Feb 21, 2014
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

First claim

What is claimed is:

1. A method of forming a device, the method comprising:
providing a die having a passivation layer formed thereon and a polymer layer over the passivation layer, the die further having a conductive layer over the polymer layer, the conductive layer extending through openings in the passivation layer and the polymer layer such that the conductive layer is in electrical contact with underlying conductive pads;
mounting the die on a carrier;
forming a molding compound over the conductive layer and along sidewalls of the die; and
planarizing the molding compound and the conductive layer to remove the conductive layer over the polymer layer and to form pillars from the conductive layer extending through the polymer layer.

2. The method of claim 1 , wherein the providing comprises:
forming the passivation layer over the die, the passivation layer having openings over respective ones of the conductive pads;
forming the polymer layer over the passivation layer, the polymer layer having openings over respective ones of the conductive pads;
forming a liner over the polymer layer and in the openings; and
forming the conductive layer over liner, the conductive layer being in electrical contact with the conductive pads.

3. The method of claim 1 , wherein the providing comprises forming a layer of polymer material, and patterning the layer of polymer material to form openings over respective ones of the conductive pads, thereby forming the polymer layer, the openings having tapered sidewalls with an angle of about 5° to about 30°.

4. The method of claim 1 , wherein the planarizing comprises thinning the conductive layer to a height above the conductive pads of about 2 μm to about 5 μm.

5. The method of claim 1 , wherein a width of the pillars increases as the pillars extend away from the conductive pads.

6. The method of claim 1 , further comprising forming a redistribution layer over the polymer layer after the planarizing.

7. The method of claim 6 , wherein the forming the redistribution layer comprises forming the redistribution layer over the molding compound.

8. A method of forming a device, the method comprising:
providing a die having a passivation layer formed thereon, the passivation layer having first openings over conductive pads;
forming a polymer layer covering the passivation layer, the polymer layer having second openings over the conductive pads;
forming one or more conductive layers over the polymer layer, the one or more conductive layers extending through the first openings and the second openings;
mounting the die on a carrier;
forming a molding compound over the one or more conductive layers; and
planarizing an upper surface of the molding compound and the one or more conductive layers, thereby forming conductive pillars in respective ones of the first openings and second openings.

9. The method of claim 8 , wherein forming the molding compound comprises forming the molding compound along sidewalls of the die.

10. The method of claim 8 , further comprising singulating the die from a wafer.

11. The method of claim 8 , wherein the second openings having tapered sidewalls with an angle of about 5° to about 30°.

12. The method of claim 8 , wherein the planarizing comprises thinning the conductive layer to a height above the conductive pads of about 2 μm to about 5 μm.

13. The method of claim 8 , wherein a width of the conductive pillars increases as the pillars extend away from the conductive pads.

14. A method of forming a device, the method comprising:
providing a die having a first insulating layer formed thereon, the first insulating layer having first openings over conductive pads;
forming a second insulating layer covering the first insulating layer, the second insulating layer having second openings over the conductive pads;
forming one or more conductive layers over the second insulating layer, the one or more conductive layers extending through the first openings and the second openings;
forming a molding compound over the one or more conductive layers; and
planarizing an upper surface of the molding compound and the one or more conductive layers, thereby forming conductive pillars in respective ones of the first openings and second openings.

15. The method of claim 14 , further comprising forming a redistribution layer over the second insulating layer after the planarizing.

16. The method of claim 15 , wherein the forming the redistribution layer comprises forming the redistribution layer over the molding compound.

17. The method of claim 14 , wherein the second insulating layer comprises a polymer layer.

18. The method of claim 14 , further comprising singulating the die from a wafer.

19. The method of claim 14 , further comprising attaching the die to a carrier substrate.

20. The method of claim 14 , wherein a width of the conductive pillars increases as the pillars extend away from the conductive pads.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Ho Ming-Che
• Wu Yi-Wen
• Hwang Chien Ling
• Kuo Hung-Jui
• Liu Chung-Shi

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/01251

  Changing the shapes of bumps · CPC title

• H10W72/874

  On different surfaces · CPC title