Method of protecting an interlayer dielectric layer and structure formed thereby

Patent metadata

Field	Value
Publication number	US-9263252-B2
Application number	US-201313735949-A
Country	US
Kind code	B2
Filing date	Jan 7, 2013
Priority date	Jan 7, 2013
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first gate structure;
a second gate structure;
an interlayer dielectric (ILD) layer over a substrate for electrically insulating the first gate structure from the second gate structure;
a protective layer on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, wherein a top surface of the protective layer is level with a top surface of the first gate structure and a top surface of the second gate structure, a thickness of the protective layer is about 20% to about 100% of a thickness of the ILD layer, and the protective layer comprises silicon carbon nitride (SiCN); and
a contact etch stop layer (CESL) between the substrate and the ILD layer, wherein the protective layer contacts a sidewall of the CESL.

2. The semiconductor device of claim 1 , wherein the protective layer has a thickness of about 10 nanometers (nm) to about 20 nm.

3. The semiconductor device of claim 1 , further comprising:
a first electrode layer in the first gate structure; and
a second electrode layer in the second gate structure, wherein the protective layer has a different etch selectivity than the first electrode layer and the second electrode layer.

4. The semiconductor device of claim 1 , wherein a width of the ILD layer ranges from about 25 nanometers (nm) to about 75 nm.

5. The semiconductor device of claim 1 , wherein at least one of the first gate structure or the second gate structure is a replacement gate structure.

6. The semiconductor device of claim 1 , wherein a width of the protective layer is equal to a width of the ILD layer.

7. The semiconductor device of claim 1 , further comprising a silicide region between the ILD layer and the substrate.

8. A method of protecting an interlayer dielectric (ILD) layer, the method comprising:
forming a gate structure over a substrate;
forming the ILD layer over the substrate;
forming a cavity in a top portion of the ILD layer;
filling the cavity with a protective layer formed over the ILD layer and the gate structure, wherein the protective layer is in direct contact with the gate structure, and the protective layer comprising silicon carbon nitride (SiCN); and
planarizing the protective layer, wherein a top surface of the planarized protective layer is level with a top surface of the gate structure; and
replacing the gate structure following planarizing the protective layer.

9. The method of claim 8 , wherein the forming the cavity in the top portion of the ILD layer comprises etching the ILD layer to a pre-determined depth.

10. The method of claim 8 , wherein the forming the cavity comprises forming the cavity having a depth of about 10 nanometers (nm) to about 20 nm.

11. The method of claim 8 , wherein the filling the cavity comprises forming the protective layer having a different etch selectivity than the ILD layer.

12. The method of claim 8 , further comprising performing a metallization process after the planarization of the protective layer.

13. The method of claim 8 , further comprising forming a silicide region on the substrate, wherein the ILD layer is between a bottom of the cavity and the silicide region.

14. The method of claim 8 , wherein forming the cavity comprises forming the cavity having a depth equal to greater than about 20% of a thickness of the ILD layer.

15. A method of protecting an interlayer dielectric (ILD) layer, the method comprising:
forming a gate structure over a substrate, wherein the gate structure comprises a dummy gate electrode;
forming the ILD layer over the substrate;
recessing a top portion of the ILD layer;
forming a protective layer formed over the recessed ILD layer and over the gate structure, wherein the protective layer directly contacts a top surface of the dummy gate electrode; and
planarizing the protective layer, wherein a top surface of the planarized protective layer is level with a top surface of the gate structure.

16. The method of claim 15 , further comprising replacing the gate structure following planarizing the protective layer.

17. The method of claim 15 , wherein forming the protective layer comprises forming the protective layer comprising silicon carbon nitride (SiCN).

18. The method of claim 15 , further comprising forming a contact etch stop layer (CESL) over the substrate, wherein forming the CESL comprises forming the CESL between the ILD and the substrate.

19. The method of claim 18 , wherein forming the protective layer comprises forming the protective layer in contact with a sidewall of the CESL.

20. The method of claim 18 , wherein planarizing the protective layer comprises exposing a top surface of the CESL between the gate structure and the protective layer.

Assignees

• Chang Chun-Wei
• Lin Yi-An
• Chen Neng-Kuo
• Sun Sey-Ping
• Wann Clement Hsingjen
• Huang Yu-Lien
• Taiwan Semiconductor Mfg

Inventors

• Chang Chun-Wei
• Lin Yi-An
• Chen Neng-Kuo
• Sun Sey-Ping
• Wann Clement Hsingjen
• Huang Yu-Lien

Classifications

• H10P14/662 Primary

  Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H01L21/022 Primary

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic