Memory having buried digit lines and methods of making the same

Patent metadata

Field	Value
Publication number	US-9263095-B2
Application number	US-201313953495-A
Country	US
Kind code	B2
Filing date	Jul 29, 2013
Priority date	Mar 10, 2010
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F 2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.

First claim

The invention claimed is:

1. A memory cell comprising:
a storage device having a horizontal planar footprint, wherein the horizontal planar footprint of the storage device is the X-Y plane of a horizontal cross section of the storage device;
a vertical access device electrically coupled to the storage device and having a horizontal planar footprint, wherein the horizontal planar footprint of the vertical access device is the X-Y plane of a horizontal cross section of the vertical access device;
a word line electrically coupled to the vertical access device; and
a buried digit line electrically coupled to the vertical access device and disposed below the storage device, the word line, and the vertical access device;
wherein the horizontal planar footprint of the storage device is equivalent to the horizontal planar footprint of the vertical access device.

2. The memory cell of claim 1 , wherein the word line and the buried digit line are orthogonal to each other.

3. The memory cell of claim 1 , wherein the storage device is disposed above the vertical access device.

4. The memory cell of claim 1 , wherein the storage device is disposed above the word line.

5. The memory cell of claim 1 , wherein the storage device comprises a capacitor.

6. The memory cell of claim 1 , wherein the vertical access device comprises a finFET.

7. The memory cell of claim 6 , wherein the finFET comprises a fin, and the vertical height of the word line is greater than two times the thickness of the fin.

8. The memory cell of claim 1 , wherein the memory cell comprises at least two vertical access devices, each of which is disposed above the buried digit line.

9. The memory cell of claim 8 , wherein the memory cell comprises at least two word lines electrically coupled to the vertical access devices.

10. The memory cell of claim 1 , wherein the vertical access device comprises a source region and a drain region, the source region and the drain region being located at different heights in the vertical access device, and wherein the word line is configured to overlap both the source region and the drain region.

11. A memory array comprising:
a memory cell having two vertical access devices electrically coupled to and disposed below a storage device, wherein:
each of the two vertical access devices has a horizontal planar footprint, the horizontal planar footprint of the vertical access device being the X-Y plane of a horizontal cross section of the vertical access device;
the storage device has a horizontal planar footprint, the horizontal planar footprint of the storage device being the X-Y plane of a horizontal cross section of the storage device; and
the horizontal planar footprint of the storage device is equivalent to a combined horizontal planar footprint of the two vertical access devices comprising the sum of the horizontal planar footprint of each of the two vertical access devices;

a word line electrically coupled to the memory cell; and
a buried digit line electrically coupled to the memory cell and disposed below the memory cell and the word line.

12. The memory array of claim 11 , wherein the word line and the buried digit line are orthogonal to each other.

13. The memory array of claim 11 , wherein the word line is disposed below the storage device.

14. The memory array of claim 11 , wherein the memory array comprises dynamic random access memory (DRAM).

15. The memory array of claim 11 , wherein the memory array comprises static random access memory (SRAM).

16. The memory array of claim 11 , wherein the memory array comprises read-only memory (ROM).

17. The memory array of claim 11 , wherein the memory array comprises a first word line and a second word line parallel to one another, and wherein the first and second word lines are electrically coupled to the two vertical access devices of the memory cell.

18. The memory array of claim 11 , wherein each of the vertical access devices comprises a finFET.

19. The memory array of claim 11 , wherein the storage device comprises a capacitor.

20. A system comprising:
a processor;
an address bus;
a decoder block configured to receive and translate address information from the processor via the address bus; and
a memory array arranged to receive translated address information from the decoder block, the memory array comprising:
a plurality of memory cells, each memory cell comprising a storage device having a horizontal planar footprint, the horizontal planar footprint of the storage device being the X-Y plane of a horizontal cross section of the storage device and a vertical access device having a horizontal planar footprint, the horizontal planar footprint of the vertical access device being the X-Y plane of a horizontal cross section of the vertical access device, wherein the horizontal planar footprint of the storage device is equivalent to the horizontal planar footprint of the vertical access device;
a word line electrically coupled to the vertical access device of each memory cell; and
a buried digit line electrically coupled to the vertical access device of one of the plurality of memory cells and disposed below the plurality of memory cells and the word line.

21. The system of claim 20 , wherein the plurality of memory cells are configured in a grid formation, and wherein the address decoder block comprises a row decoder block and a column decoder block.

22. The system of claim 20 , wherein the memory array comprises DRAM, SRAM, ROM, or any combination thereof.

23. The system of claim 20 , wherein each of the plurality of memory cells comprises two vertical access devices, and wherein the horizontal planar footprint of the storage device is equivalent to a combined horizontal planar footprint of the two vertical access devices comprising a sum of the horizontal planar footprint of each of the two vertical access devices.

Assignees

• Micron Technology Inc

Inventors

• Parekh Kunal
• Hwang David
• Huang Wen Kuei
• Wang Kuo Chen
• Lin Ching Kai

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• G11C11/405 Primary

  with three charge-transfer gates, e.g. MOS transistors, per cell · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H01L29/7827

  Electricity · mapped topic