Direct memory access rate limiting in a communication device

Patent metadata

Field	Value
Publication number	US-9258257-B2
Application number	US-201313738789-A
Country	US
Kind code	B2
Filing date	Jan 10, 2013
Priority date	Jan 10, 2013
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

Rate limiting operations can be implemented at an ingress DMA unit to minimize the probability of dropped packets because of differences between the communication rates of the ingress DMA unit and a packet processing engine. The communication rate associated with each of the software ports of a communication device can be determined and an aggregate software port ingress rate can be calculated by summing the communication rate associated with each of the software ports. The transfer rate associated with the ingress DMA unit can be limited so that packets are transmitted from the ingress DMA unit to the packet processing engine at a communication rate that is at least equal to the aggregate software port ingress rate. If each software port comprises a dedicated rate-limited ingress DMA queue, packets from a rate-limited ingress DMA queue can be transmitted at the at least the communication rate of the corresponding software port.

First claim

What is claimed is:

1. A method for providing packets to a packet processing engine via an ingress direct memory access (DMA) unit of a communication device, the method comprising:
determining communication rates of a plurality of software ports of the communication device;
determining an aggregate software port ingress rate of the communication device based, at least in part, on the communication rates of the plurality of software ports; and
providing, by the ingress DMA unit, the packets received from at least a subset of the plurality of software ports to the packet processing engine at a transfer rate that is at least equal to the aggregate software port ingress rate and that does not exceed a maximum communication rate of the packet processing engine.

2. The method of claim 1 , wherein
the communication device comprises a plurality of hardware ports, and
the plurality of software ports and the plurality of hardware ports share the packet processing engine.

3. The method of claim 1 , wherein the transfer rate of the ingress DMA unit comprises at least one member selected from the group consisting of a bits per second throughput associated with the ingress DMA unit and a number of packets transferred per second by the ingress DMA unit.

4. The method of claim 1 , further comprising configuring the ingress DMA unit to limit the transfer rate for providing packets to the packet processing engine to a rate between the aggregate software port ingress rate and the maximum communication rate of the packet processing engine.

5. The method of claim 1 , wherein the communication device comprises one or more processors configured to pre-process packets received at the plurality of software ports.

6. The method of claim 1 , wherein the ingress DMA unit comprises a plurality of ingress DMA queues, wherein each of the plurality of ingress DMA queues corresponds to one or more of the plurality of software ports.

7. The method of claim 1 , wherein the ingress DMA unit comprises a plurality of ingress DMA queues, wherein each of the plurality of software ports maps to at least one of the plurality of ingress DMA queues.

8. The method of claim 1 , wherein the ingress DMA unit comprises one or more ingress DMA queues associated with the plurality of software ports, and wherein said providing, by the ingress DMA unit, the packets received from at least the subset of the plurality of software ports to the packet processing engine comprises, for a first ingress DMA queue of the one or more ingress DMA queues,
providing, from the first ingress DMA queue, packets received from a first software port to the packet processing engine at a transfer rate that is at least equal to a communication rate associated with the first software port.

9. The method of claim 1 , further comprising determining the maximum communication rate of the packet processing engine based, at least in part, on the aggregate software port ingress rate and an aggregate hardware port ingress rate.

10. The method of claim 1 , wherein the ingress DMA unit comprises one or more ingress DMA queues associated with the plurality of software ports, the method further comprising:
for a rate limiter associated with a first ingress DMA queue of the one or more ingress DMA queues,
configuring a communication rate of the rate limiter to be at least equal to a communication rate of a first software port associated with the first ingress DMA queue and less than the maximum communication rate of the packet processing engine.

11. The method of claim 1 , wherein
a communication rate associated with a first software port of the plurality of software ports is a peak ingress communication rate of the first software port; and
a communication rate associated with a first hardware port of one or more hardware ports of the communication device is a peak ingress communication rate of the first hardware port.

12. The method of claim 1 , wherein the maximum communication rate of the packet processing engine comprises at least one member selected from the group consisting of a predefined bits per second throughput of the packet processing engine and a predefined packets per second throughput of the packet processing engine.

13. The method of claim 1 , wherein if the ingress DMA unit comprises one or more ingress DMA queues associated with the plurality of software ports, the method further comprising:
determining, at the ingress DMA unit, whether to provide a packet from a first ingress DMA queue to the packet processing engine based, at least in part, on determining whether providing the packet to the packet processing engine will exceed the maximum communication rate of the packet processing engine.

14. The method of claim 13 , wherein said determining whether providing the packet to the packet processing engine will exceed the maximum communication rate of the packet processing engine comprises at least one member selected from the group consisting of:
determining whether providing the packet to the packet processing engine will cause the packet processing engine to exceed a predefined bits per second throughput threshold; and
determining whether providing the packet to the packet processing engine will cause the packet processing engine to exceed a predefined packets processed per second threshold.

15. The method of claim 1 , further comprising:
determining an aggregate hardware port ingress rate of the communication device based, at least in part, on a sum of communication rates of a plurality of hardware ports of the communication device; and
determining the maximum communication rate of the packet processing engine based, at least in part, on a sum of the aggregate software port ingress rate and the aggregate hardware port ingress rate.

16. The method of claim 1 , wherein the aggregate software port ingress rate of the communication device comprises a sum of the communication rates of the plurality of software ports.

17. The method of claim 1 , further comprising
receiving a packet in a first packet format at a first software port of the plurality of software ports;
converting the packet from the first packet format into a second packet format supported by the packet processing engine; and
providing the packet in the second packet format to the ingress DMA unit for subsequent transfer to the packet processing engine.

18. The method of claim 17 , wherein said providing the packet in the second packet format to the ingress DMA unit comprises:
providing the packet to a first ingress DMA queue of the ingress DMA unit, wherein the first ingress DMA queue is associated with the first software port.

19. The method of claim 17 , wherein the first packet format is a wireless local area network (WLAN) packet format or a universal serial bus (USB) packet format.

20. The method of claim 17 , wherein the second packet format is an Ethernet packet format.

21. The method of claim 1 , further comprising:
determining to transmit a packet, from the packet processing engine to an egress DMA unit of the communication device based, at least in part, on a transmission priority of the packet; and
determining to transmit the packet from the egress DMA unit to a first software port of the plurality of software ports based, at least in part, on a communication rate associated with the first software port.

22. The method of claim 21 ,
wherein the egress DMA unit comprises one or more rate-limited egress DMA queues associated with of the plurality o

Assignees

• Qualcomm Inc

Inventors

• Malik Rahul
• Rai Aaditya
• Banerjee Samarjeet
• Rastogi Abhishek

Classifications

• H04L49/9063 Primary

  Intermediate storage in different physical parts of a node or terminal · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title