Method for cut through forwarding data packets between electronic communication devices

Patent metadata

Field	Value
Publication number	US-9438537-B2
Application number	US-201214406954-A
Country	US
Kind code	B2
Filing date	Jul 3, 2012
Priority date	Jul 3, 2012
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

An electronic device communicates according to a network protocol that defines data packets, for example EtherCAT. The device has a processor for performing input control on incoming data packets and performing output control on outgoing data packets, and a shared FIFO buffer comprising a multiuser memory. An input unit receives input data, detects the start of a respective data packet, subdivides the data packet into consecutive segments, one segment having a predetermined number of data bytes, and transfers the segment to the FIFO buffer before the next segment has been completely received. The processor accesses, in the input control, the multiuser memory for processing the segment, and, in the output control, initiates outputting the output packet before the corresponding input data packet has been completely received. An output unit transfers the segment from the FIFO buffer, and transmits the segment to the communication medium.

First claim

The invention claimed is:

1. An electronic device comprising:
a first input unit and a first output unit configured to communicate with other devices according to a network protocol via a communication medium, the network protocol defining data packets comprising data bytes having a predetermined structure including a packet header;
a first processor configured to perform input control on incoming data packets and perform output control on outgoing data packets;
a first in first out (FIFO) buffer comprising a multiuser memory, the input of the first FIFO buffer being coupled to the first input unit and the output of the first FIFO buffer being coupled to the first output unit, the first FIFO buffer being shared between the input control and the output control via the multiuser memory, wherein
the first input unit is arranged to
receive input data comprising incoming data packets from the communication medium,
detect the start of a respective data packet,
subdivide the data bytes of the respective data packet into consecutive segments, one segment having a predetermined number of data bytes, and
transfer the segment to the first FIFO buffer before the next segment has been completely received;

the first processor is arranged to
in the input control, access the multiuser memory for processing the segment, and
in the output control, initiate outputting the output packet before the corresponding input data packet has been completely received; and

the first output unit is arranged to
transfer the segment from the first FIFO buffer to the first output unit, and
transmit the segment to the communication medium.

2. The device as claimed in claim 1 , wherein
the first input unit is arranged to
prefix metadata to the segment, and
transfer the metadata with the segment to the first FIFO buffer; and

the first processor is arranged to process the metadata.

3. The device as claimed in claim 1 , wherein the incoming packets correspond to data on a Data Link layer according to an International Organization for Standardization (ISO) layer 2 network protocol.

4. The device as claimed in claim 1 , wherein the start of a respective data packet is after a preamble and Start of Frame Delimiter (SFD) on the physical layer according to an International Organization for Standardization (ISO) layer 1 network protocol.

5. The device as claimed in claim 1 , wherein the segments have a size of 8, 16 or 24 data bytes.

6. The device as claimed in claim 1 , wherein the first processor is a reduced instruction set computer (RISC) processor.

7. The device as claimed in claim 1 , wherein the input control comprises a receiver thread and the output control comprises a transmitter thread.

8. The device as claimed in claim 1 , wherein the first processor is arranged to convert a receive attribute of incoming data into a transmit attribute.

9. The device as claimed in claim 1 , wherein the first processor is arranged to change data bytes in a segment depending on a command in the data packet being processed.

10. The device as claimed in claim 9 , wherein the first processor is arranged to process a command that writes data from the incoming packet into a memory or register in the device by parsing and analyze the incoming packet, or a command that reads data from a register or memory in device by changing the data bytes in the outgoing packet.

11. The device as claimed in claim 1 , wherein the device comprises a hardware scheduler arranged to monitor activity of the first processor and pending requests from threads, and to assign a priority pending request to the first processor or round robin if multiple pending requests are the same priority.

12. The device as claimed in claim 1 , wherein the device is a slave node device.

13. The device as claimed in claim 1 , wherein the device has a second input unit, second output unit, second FIFO buffer coupled to the first processor, the second input unit, second output unit and second FIFO buffer being arranged equal to said first input unit, first output unit and first FIFO buffer.

14. The device as claimed in claim 1 , wherein the device has a second input unit and a second output unit, a second FIFO buffer and a second processor, the second input unit, second output unit, second FIFO buffer and second processor being arranged equal to said first input unit, first output unit, first FIFO buffer and first processor.

15. The device as claimed in claim 1 , wherein the device comprises a data handling unit, and the first processor is arranged to control transferring of segments of a data packet from the first FIFO buffer to the data handling unit.

16. The device as claimed in claim 1 , wherein the device comprises a data handling unit, and the processor is arranged to control transferring of segments of a data packet from the data handling unit into the first FIFO buffer.

17. The device as claimed in claim 1 , wherein the network protocol is Ethernet for Control automation Technology (EtherCAT).

18. An integrated circuit comprising at least one electronic device according to claim 1 .

19. A method of communicating between electronic devices, the device comprising:
an input unit and an output unit for communicating with other devices according to a network protocol via a communication medium, the network protocol defining data packets comprising data bytes having a predetermined structure including a packet header;
the method comprising
performing input control on incoming data packets and performing output control on outgoing data packets;

the device comprising
a first in first out (FIFO) buffer comprising a multiuser memory, the input of the FIFO buffer being coupled to the input unit and the output of the FIFO buffer being coupled to the output unit, the FIFO buffer being shared between the input control and the output control via the multiuser memory; and

the method comprising
receiving input data comprising incoming data packets from the communication medium,
detecting the start of a respective data packet,
subdividing the data bytes of the respective data packet into consecutive segments, one segment having a predetermined number of data bytes,
transferring the segment to the FIFO buffer before the next segment has been completely received,
in the input control, accessing the multiuser memory for processing the segment,
in the output control, initiating outputting the output packet before the corresponding input data packet has been completely received,
transferring the segment from the FIFO buffer to the output unit, and
transmitting the segment to the communication medium.

20. The method as claimed in claim 19 , wherein the incoming packets correspond to data on a Data Link layer according to an International Organization for Standardization (ISO) layer 2 network protocol.

Assignees

• Edmiston Graham
• Rahamim Hezi
• Yosha Amir
• Freescale Semiconductor Inc

Inventors

• Edmiston Graham
• Rahamim Hezi
• Yosha Amir

Classifications

• H04L49/90 Primary

  Buffering arrangements · CPC title

• H04L49/9063 Primary

  Intermediate storage in different physical parts of a node or terminal · CPC title

• H04L45/66

  Layer 2 routing, e.g. in Ethernet based MAN's · CPC title