Embedded JFETs for high voltage applications

Patent metadata

Field	Value
Publication number	US-9257979-B2
Application number	US-201414166475-A
Country	US
Kind code	B2
Filing date	Jan 28, 2014
Priority date	May 25, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

First claim

What is claimed is:

1. A method comprising:
conducting a current between a source region and a drain region of a Junction Field-Effect Transistor (JFET), wherein the current comprises:
a first portion underlying a first P-type Buried Layer (PBL), wherein the first portion of the current is further conducted through a first portion of an n-well region, with the n-well region between a first p-well region and a second p-well region; and
a second portion through a second portion of the n-well region, wherein the second portion of the n-well region is between the first PBL and a second PBL;

applying a voltage to a first gate of the JFET, wherein the voltage is applied from the first gate to the first p-well region; and
applying the voltage to a second gate of the JFET, with the first gate and the second gate being on opposite sides of the source region, wherein the voltage is applied from the second gate to the second p-well region, and wherein the first portion of the current is pinched-off by first depletion regions formed due to the voltage.

2. The method of claim 1 further comprising:
applying the voltage to a third p-well region, wherein the second p-well region and the third p-well region are on a same side of the source region, and wherein the second portion of the current is pinched-off by second depletion regions formed due to the voltage.

3. The method of claim 1 , wherein the first portion of the current is pinched-off by the first depletion regions growing in a first direction parallel to a source-to-drain direction of the JFET.

4. The method of claim 3 , wherein during a period of time in which the first portion of the current is pinched-off in the first direction, the first portion of the current is not pinched-off in a second direction perpendicular to the source-to-drain direction of the JFET.

5. The method of claim 3 , wherein during a period of time in which the first portion of the current is pinched-off in the first direction, the first portion of the current is further pinched-off in a second direction perpendicular to the source-to-drain direction of the JFET.

6. The method of claim 1 , wherein the second portion of the current comprises:
a first sub-portion level with the first PBL and the second PBL; and
a second sub-portion over the first PBL and the second PBL.

7. The method of claim 1 , wherein during a period of time in which the current is pinched-off by the voltage, a first depletion region grown from the first p-well region is merged to a second depletion region grown from the second p-well region, with the first depletion region and the second depletion region comprised in the first depletion regions.

8. The method of claim 1 further comprising, during the applying the voltage to the second gate, applying the voltage to a gate electrode of a Metal-Oxide-Semiconductor (MOS) device, with the MOS device comprising the source region of the JFET as a source region of the MOS device.

9. The method of claim 1 further comprising, during the applying the voltage to the second gate, applying an additional voltage to a gate electrode of a Metal-Oxide-Semiconductor (MOS) device, with the MOS device comprising the source region of the JFET as a source region of the MOS device, and wherein the voltage and the additional voltage are different from each other.

10. The method of claim 1 , wherein the voltage is an electrical grounding voltage or a negative voltage.

11. A method comprising:
forming a buried well region of a first conductivity type over a substrate layer;
forming a first High Voltage Well (HVW) region of the first conductivity type over the buried well region;
forming an insulation region over the first HVW region;
forming a drain region of the first conductivity type on a first side of the insulation region;
forming a gate electrode on a second side of the insulation region;
forming a well region of a second conductivity type in a region adjacent to the insulation region;
forming a second HVW region of the first conductivity type overlapping a portion of the buried well region; and
forming a source region of the first conductivity type in a top region of the second HVW region.

12. The method of claim 11 , wherein the first conductivity type is n-type.

13. A method comprising:
conducting a current between a source region and a drain region of a Junction Field-Effect Transistor (JFET), wherein the current comprises:
a first portion underlying a first P-type Buried Layer (PBL), wherein the first portion of the current is further conducted through a first portion of an n-well region, with the n-well region between a first p-well region and a second p-well region, wherein the first p-well region and the second p-well region are both between the source region and the drain region; and
a second portion through a second portion of the n-well region, wherein the second portion of the n-well region is between the first PBL and a second PBL;

applying a first voltage to a first gate of the JFET, wherein the first voltage is applied from the first gate to the first p-well region; and
applying a second voltage to a to a second gate of the JFET, wherein the second voltage is applied to the second p-well region, and wherein the second portion of the current is pinched-off by depletion regions induced by the first voltage and the second voltage.

14. The method of claim 13 further comprising:
applying a third voltage to a third gate of the JFET, with the first gate and the third gate being on opposite sides of the source region, wherein the third voltage is applied from the third gate to a third p-well region, and wherein the first portion of the current is pinched-off by the depletion regions and an additional depletion region induced by the third voltage.

15. The method of claim 14 , wherein the first portion of the current is pinched-off by the depletion regions and the additional depletion region growing in a first direction parallel to a source-to-drain direction of the JFET.

16. The method of claim 15 , wherein during a period of time in which the first portion of the current is pinched-off in the first direction, the first portion of the current is not pinched-off in a second direction perpendicular to the source-to-drain direction of the JFET.

17. The method of claim 13 , wherein the first voltage is equal to the second voltage.

18. The method of claim 13 , wherein the second portion of the current comprises:
a first sub-portion level with the first PBL and the second PBL; and
a second sub-portion over the first PBL and the second PBL.

19. The method of claim 13 , wherein during a period of time in which the current is pinched-off by the first voltage and the second voltage, a first depletion region grown from the first p-well region is merged to a second depletion region grown from the second p-well region, with the first depletion region and the second depletion region being parts of the depletion regions.

20. The method of claim 13 further comprising, during the applying the first voltage to the first gate, applying the second voltage to a gate electrode of a Metal-Oxide-Semiconductor (MOS) device, with the MOS device comprising the source region of the JFET as a source region of the MOS device.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yeh Jen-Hao
• Cheng Chih-Chang
• Su Ru-Yi
• Huo Ker Hsiao
• Chen Po-Chih
• Yang Fu-Chih
• Tsai Chun-Lin

Classifications

• H03K17/223 Primary

  in field-effect transistor switches · CPC title

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D64/112

  comprising multiple field plate segments · CPC title