Power electronics interconnection for electric motor drives

US9257825B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9257825-B2
Application numberUS-201414188483-A
CountryUS
Kind codeB2
Filing dateFeb 24, 2014
Priority dateMay 31, 2011
Publication dateFeb 9, 2016
Grant dateFeb 9, 2016

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The bus bar includes a first bus bar layer formed of a first generally uniform thickness of a first bus bar conductor; a first dielectric layer overlying a top surface of the first bus bar layer; and a second bus bar layer formed of a second generally uniform thickness of a second bus bar conductor overlying a top surface of the first dielectric layer and the top surface of the first bus bar layer wherein: the first bus bar layer includes a first via for receipt of a first electrical lead of an electrical component and a second via for receipt of a second electrical lead of the electrical component and wherein: the first dielectric layer and the second bus bar layer each include a via aligned with the first via wherein the first electrical lead is extendable from beneath the first bus bar layer through the first dielectric layer and through the second bus bar layer.

First claim

Opening claim text (preview).

What is claimed as new and desired to be protected by Letters Patent of the United States is: 1. A bus bar comprising: a first bus bar layer formed of a first generally uniform thickness of a first bus bar conductor; a first dielectric layer overlying a top surface of said first bus bar layer; and a second bus bar layer formed of a second generally uniform thickness of a second bus bar conductor overlying a top surface of said first dielectric layer and said top surface of said first bus bar layer, wherein: said first bus bar layer includes a first via for receipt of a first electrical lead of a first electrical component and a second via for receipt of a second electrical lead of said electrical component; said first dielectric layer and said second bus bar layer each include a via aligned with said first via wherein said first electrical lead is extendable from beneath said first bus bar layer through said first dielectric layer and through said second bus bar layer; said second bus bar layer includes a first plurality of electrically conductive mounting tabs formed from said second bus bar layer and extending generally perpendicular to said second bus bar layer and extending away from said first bus bar layer and wherein said first bus bar layer includes a second plurality of electrically conductive mounting tabs formed from said first bus bar layer and extending generally perpendicular to said first bus bar layer and through apertures in said first dielectric layer and said second bus bar layer, with said first and second plurality of electrically conductive mounting tabs extending about an equal distance from a top surface of said second bus bar layer; said first and second plurality of electrically conductive mounting tabs each include a mounting slot extending generally perpendicular to said second bus bar layer; and each said mounting slot is sized for receiving a respective first and second plurality of connection studs of a DC-Link capacitor of a high-power converter, with said mounting tabs mechanically and electrically supporting said DC-Link capacitor when mounted into said mounting slots using said plurality of connection studs wherein said DC-Link capacitor includes said first plurality of connection studs having a first polarity coupled to said first plurality of electrically conductive mounting tabs and said second plurality of connection studs having a second polarity coupled to said second plurality of electrically conductive mounting tabs. 2. The bus bar of claim 1 wherein the DC-Link capacitor includes said first plurality of connection studs and said second plurality of connection studs, with said first plurality of connection studs mechanically secured to and electrically communicated to said first plurality of mounting tabs and said second plurality of connection studs mechanically secured to and electrically communicated to said second plurality of mounting tabs, and further comprising a second electrical component coupled to a surface of said first bus bar layer not coupled to said first dielectric layer and including said first electrical lead extending through said vias of said first and second bus bar layers and including said second electrical lead extending through said second via of said first bus bar layer, wherein said first electrical lead is electrically fused to said via of said second bus bar layer and wherein said second electrical lead is electrically fused to said second via of said first bus bar layer, wherein said first electrical lead is coupled by said second bus bar layer to said first plurality of connection studs and wherein said second electrical lead is coupled by said first bus bar layer to said second plurality of connection studs. 3. The bus bar of claim 2 further comprising a first plurality of connection couplers engaged with said first plurality of connection studs and a second plurality of connection couplers engaged with said second plurality of connection studs when said DC-Link capacitor is unmounted from said first and second pluralities of electrically conductive mounting tabs and wherein said first and second pluralities of connection couplers are biased away from a body of said DC-Link capacitor by a biasing structure to maintain an installation distance between said connection couplers and said body sufficient to permit said DC-Link capacitor to be mounted into said mounting tabs with said connection couplers installed and without interference of said connection couplers with said mounting tabs when said DC-Link capacitor is installed. 4. The bus bar of claim 3 wherein said biasing structure includes a first wave spring coupled to said first plurality of connection studs and a second wave spring coupled to said second plurality of connection studs. 5. The bus bar of claim 1 wherein a first portion of said first bus bar layer includes said second via and wherein said second bus bar layer does not overlay said first portion of said first bus bar layer. 6. The bus bar of claim 1 wherein said via of said second bus bar layer includes a first electrical communication tab formed from said second bus bar layer and interacting with said first electrical lead when it extends into said via of said second bus bar layer. 7. The bus bar of claim 6 wherein said first electrical communication tab includes a first tab portion extending generally parallel to a longitudinal axis of a portion of said first electrical lead extending through said via of said second bus bar layer, said first tab portion extending above a surface of said second bus bar layer away from said first bus bar layer. 8. The bus bar of claim 7 wherein said first tab portion extends from a periphery of said via of said second bus bar layer towards a center of said via of said second bus bar layer. 9. The bus bar of claim 8 further comprising a second tab portion starting at a point on said periphery and extending towards said center. 10. The bus bar of claim 6 wherein said second via of said first bus bar layer includes a second electrical communication tab formed from said first bus bar layer and interacting with said second electrical lead when it extends into said second via of said first bus bar layer. 11. The bus bar of claim 1 further comprising a second dielectric layer overlying said second bus bar layer, and a printed circuit board assembly (PCBA) overlying said second dielectric layer, wherein said second dielectric layer and said PCBA each include a via aligned with said first via, wherein said first electrical lead is extendable from beneath said first bus bar layer through said dielectric layers, through said second bus bar layer and into and through said PCBA. 12. The bus bar of claim 11 wherein said PCBA includes a bus bar connection via and further comprising a bus bar layer connection tab formed from a portion of one of said first and second bus bar layers with said bus bar layer connection tab engaging said bus bar connection via when said PCBA overlies said first and second bus bar layers. 13. The bus bar of claim 11 wherein said PCBA includes a second via aligned with said second via of said first bus bar layer wherein said second electrical lead is extendable from beneath said first bus bar layer through said first dielectric layer and said PCBA. 14. The bus bar of claim 13 wherein said PCBA includes a bus bar connection via and further comprising a bus bar layer connection tab formed from a portion of one of said first and second bus bar layers with said bus bar layer connection tab engaging said bus bar connection via when said PCBA overlies said first and second bus bar layers.

Assignees

Inventors

Classifications

  • H02G5/00Primary

    Installations of bus-bars · CPC title

  • specially adapted for the configuration of power bus bars · CPC title

  • Assembling terminal to elongated conductor · CPC title

  • with coating · CPC title

  • Laminated bus-bars · CPC title

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Frequently asked questions

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What does patent US9257825B2 cover?
The bus bar includes a first bus bar layer formed of a first generally uniform thickness of a first bus bar conductor; a first dielectric layer overlying a top surface of the first bus bar layer; and a second bus bar layer formed of a second generally uniform thickness of a second bus bar conductor overlying a top surface of the first dielectric layer and the top surface of the first bus bar la…
Who is the assignee on this patent?
Tesla Motors Inc
What technology area does this patent fall under?
Primary CPC classification H02G5/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 09 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).