Fin-type field effect transistor and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9257538-B2
Application number	US-201414503348-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Oct 14, 2013
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A FinFET device includes a gate dielectric layer on a substrate, a fin on the gate dielectric layer having a middle section and source and drain regions at opposite ends, and a gate structure on the middle section of the fin. The FinFET device also includes a trench in a portion of the source and drain regions and a multi-layered epitaxial structure in the trench. The multi-layered epitaxial structure includes a first epitaxial layer in direct contact with the bottom of the trench, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The first epitaxial layer is a carbon-doped silicon layer having a carbon dopant concentration of less than 4 percent by weight, the second epitaxial layer is a barrier metal layer, and the third epitaxial layer is a metal layer.

First claim

What is claimed is:

1. A method of manufacturing a fin-type field effect transistor, the method comprising:
providing a substrate having a fin;
forming a gate structure on the fin;
forming source and drain regions adjacent to the gate structure;
etching a portion of the source and drain regions to form a trench;
forming a first epitaxial layer in the trench, the first epitaxial layer being a carbon-doped silicon layer having a carbon concentration of less than 4 percent by weight;
forming a second epitaxial layer on the first epitaxial layer, the second epitaxial layer being a barrier metal layer; and
forming a third epitaxial layer on the second epitaxial layer, the third epitaxial layer being a metal layer.

2. The method of claim 1 , wherein the first epitaxial layer has a thickness in a range between 0 nm and 5 nm.

3. The method of claim 1 , wherein the second epitaxial layer has a thickness in a range between 0 nm and 3 nm.

4. The method of claim 1 , wherein the third epitaxial layer has a thickness in a range between 45 nm and 55 nm.

5. The method of claim 1 , wherein the barrier metal layer comprises a metal nitride material composed of tungsten nitride.

6. The method of claim 5 , wherein the barrier metal layer is formed by chemical vapor deposition or atomic layer deposition using WF6 and NF3 precursors.

7. The method of claim 1 , wherein the metal layer comprises a tungsten material.

8. The method of claim 1 , wherein the trench has a depth in a range between 45 nm and 55 nm.

9. The method of claim 1 , wherein the trench has a length extending in a horizontal direction relative to a surface of the fin in a range between 20 nm and 30 nm.

10. A fin-type field effect transistor (FinFET) device comprising:
a substrate;
a gate dielectric layer on the substrate;
a fin on the gate dielectric layer, the fin having a middle section and source and drain regions at opposite ends;
a trench in a portion of the source and drain regions;
a gate structure on the middle section of the fin; and
an epitaxial layer comprising:
a first epitaxial layer in the trench, the first epitaxial layer being a carbon-doped silicon layer having a carbon dopant concentration of less than 4 percent by weight;
a second epitaxial layer on the first epitaxial layer, the second epitaxial layer being a barrier metal layer; and
a third epitaxial layer on the second epitaxial layer, the third epitaxial layer being a metal layer.

11. The FinFET device of claim 10 , wherein the first epitaxial layer has a thickness in a range between 0 nm and 5 nm.

12. The FinFET device of claim 10 , wherein the second epitaxial layer has a thickness in a range between 0 nm and 3 nm.

13. The FinFET device of claim 10 , wherein the third epitaxial layer has a thickness in a range between 45 nm and 55 nm.

14. The FinFET device of claim 10 , wherein the barrier metal layer comprises a metal nitride material composed of tungsten nitride.

15. The FinFET device of claim 10 , wherein the metal layer comprises a tungsten material.

16. The FinFET device of claim 10 , wherein the trench has a depth in a range between 45 nm and 55 nm.

17. The FinFET device of claim 10 , wherein the trench has a length extending in a horizontal direction relative to a surface of the fin in a range between 20 nm and 30 nm.

Assignees

• Semiconductor Mfg Int Shanghai

Inventors

• Mieno Fumitake

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D62/117

  Shapes of semiconductor bodies · CPC title