Gate-all-around metal-oxide-semiconductor transistors with gate oxides

Patent metadata

Field	Value
Publication number	US-9257535-B2
Application number	US-201514725719-A
Country	US
Kind code	B2
Filing date	May 29, 2015
Priority date	Jan 15, 2013
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A method and structure for a semiconductor transistor, including various embodiments. In embodiments, a transistor channel can be formed between a semiconductor source and a semiconductor drain, wherein a transistor gate oxide completely surrounds the transistor channel and a transistor gate metal that completely surrounds the transistor gate oxide. Related fabrication processes are presented for similar device embodiments based on a Group III-V semiconductor material and silicon-on-insulator materials.

First claim

The invention claimed is:

1. A method for forming a semiconductor device, comprising:
providing a crystalline silicon layer overlying a first silicon dioxide layer, wherein the crystalline silicon comprises a first thickness;
oxidizing a transistor channel region of the crystalline silicon to thin the crystalline silicon at the transistor channel region to a second thickness while a semiconductor source region and a semiconductor drain region remain unoxidized;
forming a first patterned mask to cover the semiconductor source region, the semiconductor drain region, and the transistor channel region while other portions of the crystalline silicon remain exposed;
oxidizing the exposed regions of the crystalline silicon while the semiconductor source region, the semiconductor drain region, and the transistor channel region are covered by the patterned mask;
removing the first patterned mask after oxidizing the exposed regions of the crystalline silicon;
forming a second patterned mask to cover the semiconductor source region and the semiconductor drain region, and leaving the transistor channel region exposed;
etching silicon dioxide surrounding the transistor channel region to form a floating nanowire bridged between the semiconductor source region and the transistor channel region, while the semiconductor source region and the semiconductor drain region are covered by the second patterned mask, then removing the second patterned mask;
forming a transistor gate oxide on the floating nanowire wherein, in a cross section of the floating nanowire, the transistor gate oxide completely surrounds the floating nanowire;
forming a transistor gate metal on the transistor gate oxide; and
forming semiconductor source, semiconductor drain, and transistor gate metallizations.

2. The method of claim 1 , further comprising forming the transistor gate metal at the cross section to completely surround the floating nanowire and the transistor gate oxide.

3. The method of claim 1 , wherein the first thickness is about 100 nm before thinning.

4. The method of claim 1 , wherein the second thickness is between about 10 nm to about 20 nm.

5. The method of claim 1 , wherein the thinning of the silicon in the channel region determines a physical length of the transistor channel.

6. The method of claim 1 , wherein the etching silicon dioxide surrounding the transistor channel region comprising etching using a buffered hydrogen fluoride (HF) solution.

7. The method of claim 1 , wherein the forming the transistor gate oxide on the floating nanowire comprises an atomic layer deposition process.

8. A method for forming a semiconductor device, comprising:
providing a sacrificial layer on a first gallium nitride (GaN) layer, wherein the sacrificial layer comprises an InGaN alloy;
providing a patterned second GaN layer on first portions of the sacrificial layer while second portions of the sacrificial layer remain uncovered by the second GaN layer, wherein the patterned second GaN layer defines a semiconductor source region, a semiconductor drain region, and a transistor channel interposed between, and connected to, the semiconductor source region and the semiconductor drain region;
forming a dielectric layer on the second portions of the sacrificial layer;
patterning the dielectric layer, wherein a portion of the dielectric layer remains at a location lateral to the transistor channel region;
subsequent to patterning the dielectric layer, etching the sacrificial layer using an etch that undercuts the sacrificial layer from under the transistor channel region to form a floating nanowire bridged between the semiconductor source region and the transistor channel region;
after forming the floating nanowire, removing the patterned dielectric layer;
forming a transistor gate oxide on the floating nanowire wherein, in a cross section of the floating nanowire, the transistor gate oxide completely surrounds the floating nanowire;
forming a transistor gate metal on the transistor gate oxide; and
forming semiconductor source, semiconductor drain, and transistor gate metallizations.

9. The method of claim 8 , wherein:
the sacrificial layer is indium-gallium-nitride; and
the etching of the InGaN layer using an etch that removes the InGaN from under the transistor channel region further comprises exposing the InGaN layer and the second GaN layer to a light source outputting a light wavelength that is absorbed by the InGaN layer to a greater degree than it is absorbed by the second GaN layer to form photo-generated carriers in the InGaN layer such that the exposed InGaN layer can be etched at an etch rate that is higher than the second GaN layer.

10. The method of claim 8 , wherein:
the sacrificial layer is aluminum-indium-nitride (AlInN); and
further comprising exposing the InGaN layer and second GaN layer to a light wavelength of about 405 nm during the exposure of the InGaN layer and the second GaN layer to the light source.

11. The method of claim 8 , wherein:
the sacrificial layer is aluminum-indium-nitride (AlInN); and
the etching of the AlInN layer using an etch that removes the AlInN from under the transistor channel region further comprises:
after patterning the dielectric layer, oxidizing the AlInN; then
performing the etch that undercuts the patterned dielectric to remove the oxidized sacrificial layer.

12. The method of claim 8 , further comprising forming the transistor gate metal at the cross section to completely surround the floating nanowire and the transistor gate oxide.

13. The method of claim 9 , wherein the etching comprising immersion in an electrolyte.

14. The method of claim 13 , wherein the electrolyte comprise potassium hydroxide.

15. The method of claim 9 , wherein the etching comprising illumination of a wavelength of radiation that is absorbed in the InGaN layer but is transmitted through the GaN layer.

16. The method of claim 8 , wherein the transistor gate oxide is deposited on exposed GaN surfaces by an atomic layer deposition process.

Assignees

• Lee Seung-Chang
• Brueck Steven
• Feezell Daniel
• Stc Unm

Inventors

• Lee Seung-Chang
• Brueck Steven
• Feezell Daniel

Classifications

• H10P14/6312

  of Group III-V semiconductors · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P50/646

  of Group III-V materials · CPC title

• H10P50/617

  of Group III-V materials · CPC title

• H10D64/01

  Manufacture or treatment · CPC title