Integrated circuit packaging system with substrate and method of manufacture thereof

Patent metadata

Field	Value
Publication number	US-9257384-B2
Application number	US-201213488812-A
Country	US
Kind code	B2
Filing date	Jun 5, 2012
Priority date	Jun 5, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a stack substrate over the base substrate with an inter-substrate connector directly on the stack substrate and the base substrate, the inter-substrate connector having an inter-substrate connector pitch; mounting an integrated circuit over the stack substrate, the integrated circuit having an internal connector directly on the stack substrate; and attaching an external connector directly on the base substrate, the external connector having an external connector pitch greater than the inter-substrate connector pitch.

First claim

What is claimed is:

1. An integrated circuit packaging system comprising:
a base substrate;
a stack substrate over the base substrate, the stack substrate having a stack core layer having a stack hole through the stack core layer, the stack hole is bounded by a side wall of the stack core layer, a stack connector is within the stack hole of the stack core layer on the side wall of the stack core layer, first stack conductive layers are patterned on the stack core layer and the stack connector, a stack insulation is within the stack hole and the stack connector, the stack insulation is directly on the stack connector, the stack core layer, and the first stack conductive layers, the stack insulation has stack insulation holes exposing portions of the first stack conductive layers, second stack conductive layers and stack pads are patterned on the stack insulation, stack inter-layer connectors directly connect the first stack conductive layers and the second stack conductive layers in the stack insulation holes, stack protection layers fully cover the second stack conductive layers and the stack inter-layer connectors, the stack protection layers cover portions of the stack pads including a stack bottom pad and a stack top pad;
an inter-substrate connector directly on the stack bottom pad of the stack substrate and the base substrate, the inter-substrate connector having an inter-substrate connector pitch;
an integrated circuit over the stack substrate, the integrated circuit having an internal connector directly on the stack top pad of the stack substrate, the internal connector having an internal connector pitch smaller than the inter-substrate connector pitch;
an external connector directly on the base substrate, the external connector having an external connector pitch greater than the inter-substrate connector pitch;
an underfill attached to the integrated circuit and the stack substrate, the underfill covers the internal connector, the underfill is attached to only a stack substrate top side of the stack substrate; and
wherein: the stack substrate includes a stack substrate width less than a base substrate width of the base substrate; and
the integrated circuit includes an integrated circuit width less than the stack substrate width.

2. The system as claimed in claim 1 wherein the external connector includes an external connector height greater than an inter-substrate connector height of the inter-substrate connector.

3. The system as claimed in claim 1 wherein the stack substrate includes a stack substrate width less than a base substrate width of the base substrate.

4. The system as claimed in claim 1 wherein the inter-substrate connector is directly on the stack substrate and the base substrate.

5. The system as claimed in claim 1 wherein the external connector includes external connectors attached to the base substrate in a peripheral array.

6. The system as claimed in claim 1 wherein the external connector includes an external connector height greater than an inter-substrate connector height of the inter-substrate connector and an internal connector height of the inter-substrate connector.

7. The system as claimed in claim 1 wherein:
the stack substrate includes a stack substrate bottom side; and
the inter-substrate connector is directly on the stack substrate bottom side and the base substrate, the inter-substrate connector having the inter-substrate connector pitch greater than an internal connector pitch of the internal connector.

8. The system as claimed in claim 1 wherein the external connector includes external connectors attached to the base substrate in a peripheral array, the external connectors separate from each other based on the external connector pitch.

Assignees

• Park Soohan
• Yoon Sung Jun
• Stats Chippac Ltd

Inventors

• Park Soohan
• Yoon Sung Jun

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title