Coreless packaging substrate and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9257379-B2
Application number	US-201213417858-A
Country	US
Kind code	B2
Filing date	Mar 12, 2012
Priority date	Jul 8, 2011
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A coreless packaging substrate is provided which includes: a circuit buildup structure having at least a dielectric layer, at least a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the lowermost one of the at least a dielectric layer, a plurality of metal bumps formed on the uppermost one of the at least a wiring layer, and a dielectric passivation layer formed on the surface of the uppermost one of the circuit buildup structure and the metal bumps, with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip is enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.

First claim

What is claimed is:

1. A coreless packaging substrate, comprising:
a circuit buildup structure having at least a dielectric layer, at least a wiring layer formed on the at least a dielectric layer, and a plurality of conductive elements formed in the dielectric layer and electrically connected to the at least a wiring layer;
a plurality of electrical pads embedded in a lowermost one of the at least a dielectric layer for electrically connecting part of the conductive elements, wherein the electrical pads are exposed from a surface of the lowermost one of the at least a dielectric layer;
a plurality of copper bumps formed on an uppermost one of the at least a wiring layer, and each having a copper column portion and a copper wing portion integrally formed on the copper column portion, wherein the copper wing portion of each of the copper bumps is greater in diameter than the copper column portion; and
a dielectric passivation layer formed on an uppermost one of the at least a dielectric layer, the uppermost one of the at least a wiring layer, and the copper bumps, with an entire top surface of the copper wing portion of each of the copper bumps exposed from the dielectric passivation layer,
wherein the exposed top surface of the copper wing portion of each of the copper bumps directly contacts and is electrically connected with solder bumps of a semiconductor chip,
the dielectric passivation layer is the same in width as the uppermost one of the at least a dielectric layer, and
the copper bumps are free from protruding from the dielectric passivation layer.

2. The coreless packaging substrate of claim 1 , wherein the at least a wiring layer is embedded in the at least a dielectric layer.

3. The coreless packaging substrate of claim 1 , wherein the conductive elements are conductive vias or conductive columns.

4. The coreless packaging substrate of claim 1 , wherein exposed surfaces of the electrical pads are level with or lower than a surface of the lowermost one of the at least a dielectric layer.

5. The coreless packaging substrate of claim 1 , wherein the exposed top surface of the copper wing portion of each of the copper bumps is even with a surface of the dielectric passivation layer.

Assignees

• Tseng Tzyy-Jang
• Ho Chung-W
• Unimicron Technology Corp

Inventors

• Tseng Tzyy-Jang
• Ho Chung-W

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10P72/7426

  used as a support during build up manufacturing of active devices · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title