System and method to process horizontally aligned graphite nanofibers in a thermal interface material used in 3D chip stacks

Patent metadata

Field	Value
Publication number	US-9257359-B2
Application number	US-201113188572-A
Country	US
Kind code	B2
Filing date	Jul 22, 2011
Priority date	Jul 22, 2011
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes placing a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip.

First claim

The invention claimed is:

1. A chip stack comprising:
a first semiconductor chip and a second semiconductor chip, the second semiconductor chip mounted above the first semiconductor chip, wherein the first and second semiconductor chips are substantially identical in outline and are each rectangular in plan view;
a thermal interface material pad between the first and second semiconductor chips, the entire thermal interface material pad comprising four portions,
wherein the first portion and the second portion are shaped as acute isosceles trapezoids and comprise nanofibers aligned substantially only perpendicularly to the parallel sides of the first portion and the second portion, the shorter parallel sides of the first portion and the second portion abutting each other;
wherein the third portion and the fourth portion are shaped as isosceles right triangles and comprise nanofibers aligned substantially only perpendicularly to the hypotenuses of the third portion and the fourth portion; the right-angled vertices of the third portion and the fourth portion abutting respective ends of the shorter parallel sides of the first portion and the second portion;
the longer parallel sides of the first portion and the second portion extending to cover respective long edges of the first and second semiconductor chips, and the hypotenuses of the third portion and the fourth portion extending to cover respective short edges of the first and second semiconductor chips.

2. The chip stack of claim 1 , wherein the portions of the thermal interface material pads extend beyond the edges of the first and second semiconductor chips, in order to contact heat sinks adjacent to the first and second semiconductor chips.

Assignees

• Kuczynski Joseph
• Sinha Arvind K
• Splittstoesser Kevin A
• Tofil Timothy J
• IBM

Inventors

• Kuczynski Joseph
• Sinha Arvind K
• Splittstoesser Kevin A
• Tofil Timothy J

Classifications

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/856

  Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15) · CPC title

• H10W40/255

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

• H10W40/251

  Organics · CPC title