Semiconductor device and method for forming the same

Patent metadata

Field	Value
Publication number	US-9257323-B2
Application number	US-201313894605-A
Country	US
Kind code	B2
Filing date	May 15, 2013
Priority date	Mar 11, 2013
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A semiconductor device includes a substrate and a gate structure formed over the substrate. The semiconductor device further includes an insulator feature formed in the substrate. The insulator feature includes an insulating layer and a capping layer over the insulating layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a transistor comprising a gate structure over the substrate; and
an insulator feature in the substrate, wherein the insulator feature comprises:
an insulating layer having a first thickness; and
a capping layer, having a second thickness different from the first thickness, over the insulating layer, wherein a bottom surface of the gate structure contacts a top surface of the capping layer, and wherein a sidewall of the insulator feature comprises:
a first portion disposed at a first angle; and
a second portion over and connected to the first portion and disposed at a second angle, wherein the first angle and the second angle are different, and wherein an interface between the insulating feature and the capping layer intersects the second portion.

2. The device of claim 1 wherein the insulating layer is silicon oxide.

3. The device of claim 1 wherein the capping layer is SiN, SiCN, SiON, SiC, Si-rich oxide, or combinations thereof.

4. The device of claim 1 wherein the first thickness ranges from about 5 nm to about 50 nm, and wherein the second thickness ranges from about 3 nm to about 45 nm.

5. The device of claim 1 wherein a ratio of the second thickness to the first thickness ranges from about 0.01:1 to about 0.15:1.

6. The device of claim 1 wherein the second thickness is less than the first thickness.

7. The device of claim 1 wherein a ratio of an etching rate of the capping layer to an etching rate of the insulating layer, in a diluted hydrofluoric acid (DHF) solution, is less than about 1:2.

8. The device of claim 1 wherein a ratio of an etching rate of the capping layer to an etching rate of the insulating layer, in a diluted hydrofluoric acid (DHF) solution, is less than about 1:100.

9. The device of claim 1 , wherein the second portion is substantially perpendicular to a surface of the substrate.

10. A semiconductor device, comprising:
a substrate;
a patterned gate structure over the substrate;
a recess in the substrate;
a first dielectric layer formed in the recess and filling more than half a depth of the recess; and
a second dielectric layer formed over the first dielectric layer in the recess, wherein the second dielectric layer comprises a material different from a material of the first dielectric layer, and wherein the patterned gate structure is disposed directly over a top surface of the second dielectric layer.

11. The device of claim 10 wherein the second dielectric layer has a dielectric constant higher than a dielectric constant of the first dielectric layer.

12. The device of claim 10 wherein the first dielectric layer is O-containing material and the second dielectric layer is N-containing material.

13. The device of claim 10 wherein the second dielectric layer has a thickness less than a thickness of the first dielectric layer.

14. The device of claim 10 wherein the patterned gate structure includes a patterned gate dielectric and a patterned gate electrode.

15. The device of claim 10 wherein a ratio of a thickness of the second dielectric layer to a thickness of the first dielectric layer ranges from about 0.01 to about 0.15.

16. A semiconductor device comprising:
a semiconductor substrate;
an isolation region in the semiconductor substrate, wherein the isolation region comprises:
a first dielectric layer; and
a second dielectric layer over the first dielectric layer, wherein an etching resistance of the second dielectric layer is greater than an etching resistance of the first dielectric layer in a diluted hydrofluoric acid (DHF) solution; and

a transistor comprising a gate structure over the semiconductor substrate and the isolation region, wherein a bottom surface of the gate structure contacts a top surface of the second dielectric layer.

17. The semiconductor device of claim 16 , wherein the second dielectric layer has a dielectric constant higher than a dielectric constant of the first dielectric layer.

18. The semiconductor device of claim 16 , wherein the isolation region is disposed between two adjacent portions of the semiconductor substrate, and wherein the bottom surface of the gate structure contacts top surfaces of the two adjacent portions of the semiconductor substrate.

19. The semiconductor device of claim 16 , further comprising a second isolation region in the semiconductor substrate, wherein the second isolation region comprises:
a third dielectric layer; and
a fourth dielectric layer over the third dielectric layer, wherein an etching resistance of the fourth dielectric layer is greater than an etching resistance of the third dielectric layer in a DHF solution, and wherein the bottom surface of the gate structure contacts a top surface of the third dielectric layer.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Huang Yu-Lien
• Lee Tung Ying
• Lin Pei-Yi
• Fan Chun-Hsiang
• Yu sheng-wen
• Chen Neng-Kuo
• Tsai Ming-Huan

Classifications

• H10D84/8314

  the IGFETs characterised by having gate insulating layers with different properties · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P95/064

  the removal being chemical etching · CPC title

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title