Methods of forming silicon nitride spacers

Patent metadata

Field	Value
Publication number	US-9257293-B2
Application number	US-201414205673-A
Country	US
Kind code	B2
Filing date	Mar 12, 2014
Priority date	Mar 14, 2013
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

Embodiments of methods of forming silicon nitride spacers are provided herein. In some embodiments, a method of forming silicon nitride spacers atop a substrate includes: depositing a silicon nitride layer atop an exposed silicon containing layer and an at least partially formed gate stack disposed atop a substrate; modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine; and removing the modified portion of the silicon nitride layer by performing a wet cleaning process to form the silicon nitride spacers, wherein the wet cleaning process removes the modified portion of the silicon nitride layer selectively to the silicon containing layer.

First claim

The invention claimed is:

1. A method of forming silicon nitride spacers atop a substrate, comprising:
depositing a silicon nitride layer atop an exposed silicon containing layer and an at least partially formed gate stack disposed atop a substrate;
modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine; and
removing the modified portion of the silicon nitride layer by performing a wet cleaning process to form the silicon nitride spacers, wherein the wet cleaning process removes the modified portion of the silicon nitride layer selectively to the silicon containing layer.

2. The method of claim 1 , further comprising:
partially etching the silicon nitride layer by exposing the silicon nitride layer to a fluorine containing plasma.

3. The method of claim 1 , wherein the silicon nitride layer is modified to a depth of about 1 to about 2 nm atop a sidewall of the at least partially formed gate stack and to a depth of about 2 to about 8 nm atop the exposed silicon containing layer.

4. The method of claim 1 , further comprising:
subsequent to removing the modified portion of the silicon nitride layer, repeatedly modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine and subsequently removing the modified portion of the silicon nitride layer by performing a wet cleaning process until the silicon nitride spacers having desired dimensions are formed.

5. The method of claim 1 , wherein the silicon nitride spacers are formed to a thickness of at least 3 nm.

6. The method of claim 1 , wherein the wet cleaning process comprises exposing the modified portion of the silicon nitride layer to an aqueous solution containing hydrofluoric (HF) acid or phosphoric (H 3 PO 4 ) acid.

7. The method of claim 1 , wherein the hydrogen or helium containing plasma is formed from a process gas comprising one of helium (He) gas, hydrogen (H 2 ) gas, ammonia (NH 3 ), or methane (CH 4 ).

8. The method of claim 1 , wherein a depth of the portion of the silicon nitride layer modified by the hydrogen or helium containing plasma is controlled by adjusting at least one of an amount of power coupled to the plasma, a pressure maintained in a process chamber utilized to perform the modification of the silicon nitride layer or a temperature of the substrate.

9. The method of claim 1 , further comprising:
subsequent to removing the modified portion of the silicon nitride layer, performing an implantation process to implant an arsenic (As) containing material or a phosphorous (P) containing material in the exposed silicon containing layer to form a n-type MOSFET device or to implant a boron difluoride (BF 2 ) in the exposed silicon containing layer to form a p-type MOSFET device.

10. The method of claim 1 , further comprising:
subsequent to removing the modified portion of the silicon nitride layer forming an epitaxial layer atop the silicon containing layer.

11. The method of claim 1 , wherein the exposed silicon containing layer comprises one of crystalline silicon (Si) or crystalline silicon oxide (SiO 2 ).

12. A method of forming silicon nitride spacers atop a substrate, comprising:
depositing a silicon nitride layer atop an exposed silicon containing layer and an at least partially formed gate stack disposed atop a substrate;
modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine, wherein a depth of the portion of the silicon nitride layer modified by the hydrogen or helium containing plasma is controlled by adjusting at least one of an amount of power coupled to the plasma, a pressure maintained in a process chamber utilized to perform the modification of the silicon nitride layer or a temperature of the substrate; and
removing the modified portion of the silicon nitride layer by exposing the modified portion of the silicon nitride layer to an aqueous solution containing hydrofluoric (HF) acid or phosphoric (H 3 PO 4 ) acid to form the silicon nitride spacers, wherein the aqueous solution removes the modified portion of the silicon nitride layer selectively to the silicon containing layer.

13. A computer readable medium having instructions stored thereon that, when executed, cause a method of forming silicon nitride spacers atop a substrate to be performed in a process chamber, the method comprising:
depositing a silicon nitride layer atop an exposed silicon containing layer and an at least partially formed gate stack disposed atop a substrate;
modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine; and
removing the modified portion of the silicon nitride layer by performing a wet cleaning process to form the silicon nitride spacers, wherein the wet cleaning process removes the modified portion of the silicon nitride layer selectively to the silicon containing layer.

14. The computer readable medium of claim 13 , further comprising:
partially etching the silicon nitride layer by exposing the silicon nitride layer to a fluorine containing plasma.

15. The computer readable medium of claim 13 , wherein the silicon nitride layer is modified to a depth of about 1 to about 2 nm atop a sidewall of the at least partially formed gate stack and to a depth of about 2 to about 8 nm atop the exposed silicon containing layer.

16. The computer readable medium of claim 13 , further comprising:
subsequent to removing the modified portion of the silicon nitride layer, repeatedly modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine and subsequently removing the modified portion of the silicon nitride layer by performing a wet cleaning process until the silicon nitride spacers having desired dimensions are formed.

17. The computer readable medium of claim 13 , wherein the silicon nitride spacers are formed to a thickness of at least 3 nm.

18. The computer readable medium of claim 13 , wherein the wet cleaning process comprises exposing the modified portion of the silicon nitride layer to an aqueous solution containing hydrofluoric (HF) acid or phosphoric (H 3 PO 4 ) acid.

19. The computer readable medium of claim 13 , wherein the hydrogen or helium containing plasma is formed from a process gas comprising one of helium (He) gas, hydrogen (H 2 ) gas, ammonia (NH 3 ), or methane (CH 4 ).

20. The computer readable medium of claim 13 , wherein a depth of the portion of the silicon nitride layer modified by the hydrogen or helium containing plasma is controlled by adjusting at least one of an amount of power coupled to the plasma, a pressure maintained in a process chamber utilized to perform the modification of the silicon nitride layer or a temperature of the substrate.

Assignees

• Applied Materials Inc

Inventors

• Posseme Nicolas
• Joubert Olivier
• David Thibaut
• Lill Thorsten

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10P50/242 Primary

  of Group IV materials · CPC title

• H10D30/608

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title

• H10D30/0275

  forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions · CPC title