Alternate control settings

Patent metadata

Field	Value
Publication number	US-9257162-B2
Application number	US-201213525567-A
Country	US
Kind code	B2
Filing date	Jun 18, 2012
Priority date	Jun 18, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

An integrated circuit, that may be a part of an electronic system, may include a first set of storage cells to store settings and a second set of storage cells to store alternate settings. At least one control cell may also be included in the integrated circuit. The at least one control cell may indicate whether to use the settings stored in the first set of storage cells, or the alternate settings stored in the second set of storage cells, to control one or more operating parameters of the integrated circuit. Methods for using the alternate setting are also described.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first set of storage cells to store a first set of settings to configure a functional circuit at a first time;
a second set of storage cells to store a second set of settings to reconfigure the functional circuit at a second time that is later than the first time; and
at least one control cell comprising a fuse link which may be set to a first setting to use the first set of settings stored in the first set of storage cells, or the second set of settings stored in the second set of storage cells, to control one or more operating parameters of the functional circuit, wherein configuration or reconfiguration of the functional circuit is achieved by providing the settings already stored in the first set of storage cells or the alternate settings already stored in the second set of storage cells to the functional circuit without changing the first set of storage cells or the second set of storage cell during the configuration or the reconfiguration;
a multiplexer, controlled by an output of the at least one control cell, and having a first set of inputs coupled to outputs of the first set of storage cells, and a second set of inputs coupled to outputs of the second set of storage cells;
wherein the outputs of the multiplexer control the one or more operating parameters of the functional circuit.

2. The integrated circuit of claim 1 , wherein at least one of, the first set of storage cells, the second set of storage cells, or the at least one control cell, comprise non-volatile cells.

3. The integrated circuit of claim 1 , wherein at least one of, the first set of storage cells, the second set of storage cells, or the at least one control cell, comprise one-time programmable cells.

4. The integrated circuit of claim 1 , wherein at least one of, the first set of storage cells, the second set of storage cells, or the at least one control cell, comprise fuse links or anti-fuse links.

5. The integrated circuit of claim 1 , further comprising a third set of storage cells to store additional settings to reconfigure the functional circuit at a third time, wherein the additional settings control additional operating parameters of the functional circuit.

6. The integrated circuit of claim 1 , further comprising:
an array of one-time programmable, non-volatile, memory cells, wherein the array includes the first set of storage cells and the second set of storage cells; and
a control circuit to access the array based on a value of the at least one control cell and to write values, based on information accessed from the array, into one or more registers, to control the one or more operating parameters of the functional circuit.

7. The integrated circuit of claim 1 , further comprising:
an array of one-time programmable, non-volatile, memory cells, wherein the array includes the first set of storage cells and the second set of storage cells; and
address lines coupled to the array to control which memory cells of the array are accessed;
wherein a state of the at least one control cell determines a state of the address lines.

8. An electronic system comprising:
a processor to generate memory control commands;
a memory, coupled to the processor; and
an input/output circuit, coupled to the processor;
wherein at least one of, the processor, the memory, or the input/output circuit, comprise:
a first set of storage cells to store a first set of settings to configure a functional circuit at a first time;
a second set of storage cells to store a second set of settings to reconfigure the functional circuit at a second time that is later than the first time; and
at least one control cell comprising a fuse link which may be set to a first setting to use the first set of settings stored in the first set of storage cells, or the second set of settings stored in the second set of storage cells, to control one or more operating parameters of the functional circuit, wherein configuration or reconfiguration of the functional circuit is achieved by providing the settings already stored in the first set of storage cells or the alternate settings already stored in the second set of storage cells to the functional circuit without changing the first set of storage cells or the second set of storage cells during the configuration or the reconfiguration;
a multiplexer, controlled by an output of the at least one control cell, and having a first set of inputs coupled to outputs of the first set of storage cells, and a second set of inputs coupled to outputs of the second set of storage cells;
wherein the outputs of the multiplexer control the one or more operating parameters of the functional circuit.

9. The electronic system of claim 8 , wherein at least one of the first set of storage cells, the second set of storage cells, or the at least one control cell, comprise non-volatile cells.

10. The electronic system of claim 8 , wherein at least one of the first set of storage cells, the second set of storage cells, or the at least one control cell, comprise one-time programmable cells.

11. The electronic system of claim 8 , wherein at least one of, the first set of storage cells, the second set of storage cells, or the at least one control cell, comprise fuse links or anti-fuse links.

12. The electronic system of claim 8 , wherein the at least one of, the processor, the memory, or the input/output circuit, further comprise:
a third set of storage cells to store additional settings to reconfigure the functional circuit at a third time, wherein the additional settings control additional operating parameters of the functional circuit.

13. The electronic system of claim 8 , wherein the at least one of, the processor, the memory, or the input/output circuit, further comprise:
an array of one-time programmable, non-volatile, memory cells, wherein the array includes the first set of storage cells and the second set of storage cells; and
a control circuit to access the array based on a value of the at least one control cell and to write values, based on information accessed from the array, into one or more registers, to control the one or more operating parameters of the functional circuit.

14. The electronic system of claim 8 , wherein the at least one of the processor, the memory, or the input/output circuit further comprise:
an array of one-time programmable, non-volatile, memory cells, wherein the array includes the first set of storage cells and the second set of storage cells; and
address lines coupled to the array to control which memory cells of the array are accessed;
wherein a state of the at least one control cell determines a state of the address lines.

Assignees

• Walker Julie M
• Rivers Doyle
• Intel Corp

Inventors

• Walker Julie M
• Rivers Doyle

Classifications

• G11C17/165

  Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002) · CPC title

• G11C7/20 Primary

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C16/20

  Initialising; Data preset; Chip identification · CPC title

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title