Shared memory access using independent memory maps

Patent metadata

Field	Value
Publication number	US-9256545-B2
Application number	US-201213471558-A
Country	US
Kind code	B2
Filing date	May 15, 2012
Priority date	May 15, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A method includes defining a first mapping, which translates between logical addresses and physical storage locations in a memory with a first mapping unit size, for accessing the memory by a first processing unit. A second mapping is defined, which translates between the logical addresses and the physical storage locations with a second mapping unit size that is different from the first mapping unit size, for accessing the memory by a second processing unit. Data is exchanged between the first and second processing units via the memory, while accessing the memory by the first processing unit using the first mapping and by the second processing unit using the second mapping.

First claim

The invention claimed is:

1. A method, comprising:
defining a first mapping, which translates between specific logical addresses and respective specific physical storage locations in a memory with a first mapping unit size, for accessing the memory by a first processing unit serving as a host processor having an internal data caching space;
defining a second mapping, which translates between the specific logical addresses and the respective specific physical storage locations with a second mapping unit size that is different from the first mapping unit size, for accessing the memory by a second processing unit of a network interface card (NIC) serving the host processor, wherein the NIC has a smaller internal storage space than the host processor; and
exchanging data between the first and second processing units via the memory, while accessing the memory by the first processing unit using the first mapping and by the second processing unit using the second mapping,
wherein defining the first mapping comprises identifying a constraint of the second processing unit in accessing the memory, and defining the first mapping unit size so as to enable the second processing unit to follow the constraint.

2. The method according to claim 1 , wherein exchanging the data comprises communicating by the host processor over a communication network via the NIC.

3. The method according to claim 2 , wherein the second mapping unit size is larger than the first mapping unit size.

4. The method according to claim 2 , wherein the second mapping unit size is smaller than the first mapping unit size.

5. The method according to claim 1 , wherein defining the first mapping comprises identifying a constraint of the first processing unit in accessing the memory, and defining the first mapping unit size so as to meet the constraint.

6. The method according to claim 5 , wherein defining the first mapping comprises choosing to define the first mapping unit size upon detecting that the constraint is stricter in the first processing unit than in the second processing unit.

7. The method according to claim 1 , wherein exchanging the data comprises writing the data from the first processing unit to the memory using the first mapping unit size, and reading the data from the memory to the second processing unit using the second mapping unit size.

8. A method, comprising:
defining a first mapping, which translates between specific logical addresses and respective specific physical storage locations in a memory with a first mapping unit size, for accessing the memory by a first processing unit serving as a host processor having an internal data caching space;
defining a second mapping, which translates between the specific logical addresses and the respective specific physical storage locations with a second mapping unit size that is different from the first mapping unit size, for accessing the memory by a second processing unit of a network interface card (NIC) serving the host processor, wherein the NIC has a smaller internal storage space than the host processor; and
exchanging data between the first and second processing units via the memory, while accessing the memory by the first processing unit using the first mapping and by the second processing unit using the second mapping,
wherein defining the first and second mappings comprises automatically identifying a largest mapping data unit size that is usable by one of the first and second processing units, and defining the first and second mappings based on the largest mapping data unit size.

9. The method according to claim 8 , wherein identifying the largest mapping data unit size comprises identifying an available memory area in the one of the first and second processing units.

10. The method according to claim 1 , wherein accessing the memory comprises applying the first mapping by a memory management unit that is external to the first processing unit and is connected between the first processing unit and the memory.

11. The method according to claim 1 , wherein accessing the memory comprises applying the first or the second mapping by performing a cascade of two or more address translations.

12. Apparatus, comprising:
a memory;
a first processing unit, which serves as a host processor having an internal data caching space and is configured to access the memory using a first mapping that translates between specific logical addresses and respective specific physical storage locations in the memory with a first mapping unit size; and
a second processing unit of a network interface card (NIC) serving the host processor and having a smaller internal storage space than the host processor, which is configured to exchange data with the first processing unit via the memory, by accessing the memory using a second mapping that translates between the specific logical addresses and the respective specific physical storage locations with a second mapping unit size that is different from the first mapping unit size, while the first processing unit accesses the memory using the first mapping,
wherein one of the processing units is configured to identify a constraint of the second processing unit in accessing the memory, and to define the first mapping unit size so as to enable the second processing unit to follow the constraint.

13. The apparatus according to claim 12 , wherein, by exchanging the data, the host processor is configured to communicate over a communication network via the NIC.

14. The apparatus according to claim 13 , wherein the second mapping unit size is larger than the first mapping unit size.

15. The apparatus according to claim 13 , wherein the second mapping unit size is smaller than the first mapping unit size.

16. The apparatus according to claim 12 , wherein one of the processing units is configured to identify a constraint of the first processing unit in accessing the memory, and to define the first mapping unit size so as to meet the constraint.

17. The apparatus according to claim 16 , wherein the one of the processing units is configured to choose to define the first mapping unit size upon detecting that the constraint is stricter in the first processing unit than in the second processing unit.

18. The apparatus according to claim 12 , wherein the first processing unit is configured to write the data to the memory using the first mapping unit size, and wherein the second processing unit is configured to read the data from the memory using the second mapping unit size.

19. The apparatus according to claim 12 , wherein a given processing unit is configured to automatically identify a largest mapping data unit size that is usable by one of the first and second processing units, and to define the first and second mappings based on the largest mapping data unit size.

20. The apparatus according to claim 19 , wherein the given processing unit is configured to identify the largest mapping data unit size by identifying an available memory area in the one of the first and second processing units.

21. The apparatus according to claim 12 , and comprising a memory management unit, which is external to the first processing unit, is connected between the first processing unit and the memory, and is configured to apply the first mapping.

22. The apparatus according to claim 12 , wherein the first or the second mapping comprises a cascade of two or more address translations.

23. The method according to claim 1 , wherein the first mapping h

Assignees

• Raindel Shachar
• Hadas Yishai Israel
• Dubman Mike
• Mellanox Technologies Ltd

Inventors

• Raindel Shachar
• Hadas Yishai Israel
• Dubman Mike

Classifications

• G06F12/1081

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F12/10 Primary

  Address translation · CPC title

• G06F2212/652

  Page size control · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title