Controlling power gate circuitry based on dynamic capacitance of a circuit
US-9594412-B2 · Mar 14, 2017 · US
This page is not indexed by search engines while we improve data quality.
Neelakantam Naveen patents
Neelakantam Naveen holds 3 patents in our database, with recent filings and technology areas summarized below.
| Metric | Value |
|---|---|
| Total patents | 3 |
| Recent patents | 0 |
| First publication | Feb 9, 2016 |
| Latest publication | Mar 14, 2017 |
Filing trend
Year-over-year patent counts for this assignee.
Recent patents
Latest publications where this party is an assignee.
Instruction and logic for a memory ordering buffer
US-9569212-B2 · Feb 14, 2017 · US
Checkpoints associated with an out of order architecture
US-9256497-B2 · Feb 9, 2016 · US
Notable patents
Representative or frequently cited publications from precomputed assignee stats.
Controlling power gate circuitry based on dynamic capacitance of a circuit
US-9594412-B2 · Mar 14, 2017 · US
Instruction and logic for a memory ordering buffer
US-9569212-B2 · Feb 14, 2017 · US
Checkpoints associated with an out of order architecture
US-9256497-B2 · Feb 9, 2016 · US
Top CPC classifications
Most common classification codes in this portfolio.
| CPC | Patents |
|---|---|
| G06F9/30145 | 2 |
| G06F9/3842 | 2 |
| G06F9/384 | 2 |
| G06F9/38585 | 2 |
| G06F9/3856 | 2 |
Technology areas
Mapped technology topics for this assignee.
| Technology | Patents |
|---|---|
| Physics | 3 |
| Cross-Sectional Technologies | 1 |